Details of FPGA syntax

This paper records some vivado A small experiment in the use process , To help you understand better verilog Language .

About data types

The experiment purpose ： Explore register data type blocking assignments 、 Register type non blocking assignment 、 The difference between the assignment of network type .
Source file ：

module HDMI_preview(
    clk,
    reset_p,
    A,// Enter a number 
    B,// The output register is non blocking - Sequential logic 
    C,// The output register is blocked - Sequential logic 
    B1,// The output register is non blocking - Combinatorial logic 
    C1,// The output register is blocked - Combinatorial logic 
    D  // Output network type 
    );
    input clk;
    input reset_p;
    input A;
    output reg B;
    output reg C;
    output reg B1;
    output reg C1;
    output wire D;
    
    //always Block with clockticks , That is, temporal logic 
    [email protected](posedge clk or posedge reset_p)begin
        B <= A;
        C = A;
    end
    //always Block without clockticks , That is, combinatorial logic 
    [email protected](*)begin
        B1 <= A;
        C1 = A;
    end
    // Network types are all combinatorial logic 
    assign D = A; 
    
endmodule

Test code ：

`timescale 1ns / 1ps

module tb_HDMI_preview();
    reg clk;
    reg reset_p;
    reg A;
    wire B;
    wire C;
    wire B1;
    wire C1;
    wire D;

    HDMI_preview HDMI_preview(
        clk,
        reset_p,
        A,// Enter a number 
        B,// The output register is non blocking - Sequential logic 
        C,// The output register is blocked - Sequential logic 
        B1,// The output register is non blocking - Combinatorial logic 
        C1,// The output register is blocked - Combinatorial logic 
        D  // Output network type 
    );
    
    initial clk = 0;
    always#4 clk = !clk;
    
    initial begin
        reset_p = 0;
        A = 0;
        repeat(10)begin
            #10;
            A = !A;
        end
        $stop;
    end

endmodule

experimental result ：

The experimental conclusion ：

1. reg Data types can only be used in always block 、initial Block defines , But it can be non blocking assignment <=, Assignment can also be blocked =. When always Block defines the clock signal , Equivalent to sequential logic ; When always When the block has no clockticks , Equivalent to combinatorial logic , It is no different from the network type . It is equivalent to giving reg Signals provide a representation of combinatorial logic .
2. wire Data types do not wait for the clock edge to change , Non blocking assignment is not allowed , Always combinatorial logic .
3. stay always There is no difference between blocking assignment and non blocking assignment , Mainly because always The signal in the block will change its value only at the specified edge .
4. Clock signal 0s It defaults to an edge .
5. Observe B、C Initial value of signal , You can find reg The initial value of the data type signal is an indefinite value .