Risc-v instruction set explanation (7) instruction address alignment and addition and subtraction overflow processing

1. Instruction address alignment

about load/store Instructions , The address of data in memory should be aligned .

If access storage 32 Bit data , The memory address should be the same as 32 Bit data alignment , in other words ,D_PC The lowest two digits of should be 0( If data is stored in memory, it will be 32 bit In units of , Indicates that the data is 4 Byte aligned );

If access storage 16 Bit data , The memory address should be the same as 16 Bit data alignment ,D_PC The lowest bit of should be 0( Indicates that the data is 2 Byte aligned );

If access storage 8 Bit data , Because the unit of memory is a byte , That is, no alignment is required . The details are as follows: CPU How to implement the design in hardware is shown in RISC-V LSU,SRAM,GPIO modular （2）D_sram The processing of address shift in the module .

Be careful ：RISC-V Only the small end format is supported (little-endian). The comparison between the small end format and the large end format is shown in the figure 1 Shown . If different end sequences are used to store the same 32 digit 0x0A0B0C0D, The situation is shown in the picture .

The highest byte of the small end is 0x0A, The lowest byte is 0x0D;

The highest byte of the big end is 0x0D, The lowest byte is 0x0A.

If data is exchanged in systems with different end sequences , It is necessary to ensure that the transmitted data is in the form of 32 The number of digits is in . If the unit is one byte , Exchange data in different end sequence systems , There may be problems , For example, the small end here 0x0A The corresponding address (a + 3), In big end systems , The data stored in this address is 0x0D.

chart 1 Big end format , Small end format [1]

RISC-V The small end format is chosen as the end order because it is currently dominant in the business . be-all X86-32 Systems and Apple iOS, Google Android Operating system and Microsoft Windows for ARM They all use the small end format to sort addresses ( Low byte priority ) [2].

2. Add and subtract overflow treatment

As mentioned before ADD,ADDI and SUB Such instructions may overflow during calculation , Generally speaking , Hardware design ignores arithmetic overflow , therefore RISC-V Rely on software checks . The following is an example of how addition is handled ( Subtraction is similar )：

Unsigned number addition overflow （ hypothesis x6,x7 It's an unsigned number ）

ADD x5,x6,x7

BLTU x5,x6,overflow ( Jump to Processing branches with incorrect results ）

interpretative statement ：x5 by x6 and x7 And , If the sum is smaller than the addend , This indicates that addition has overflowed , That is, you can go to the branch that handles the overflow ,overflow

Signed numbers are added , It is known that imm Is a positive number

ADDI x5,x6,+imm( Positive numbers )

BLT x5,x6,overflow ( Jump to Processing branches with incorrect results ）

interpretative statement ： No matter what x6 Is it a positive number or a negative number , It adds a positive number , The result should be bigger than itself . If the x5,x6 Make a signed comparison ,x5 Less than x6, It indicates that addition has overflowed , That is, you can go to the branch that handles the overflow ,overflow

Except for the above two special cases , For general addition , The treatment is as follows

(x7 < 0)  &&  (x6 + x7 >= x6)  ||  (x7 >= 0)  &&  (x6 + x7 < x6)

ADD x5,x6,x7

SLTI x28,x7,0

SLT x29,x5,x6

BNE x28,x29,overflow ( Jump to Processing branches with incorrect results ）

interpretative statement ：

If x7 Less than 0, that x28 by 1, that x6 and x7 The sum of should be less than x6, Yes x5 and x6 Compare , If x5 Less than x6,x29 by 1, If x5 Not less than x6, That is to say, overflow , here x29 by 0.x28 It's not equal to x29, That is, you can go to the incorrect processing branch

If x7 Greater than or equal to 0, that x28 by 0, meanwhile x6 and x7 The sum of should not be less than x6, Same for x5 and x6 Compare , If x29 by 1, explain x5 Less than x6, That is to say, overflow ,x28 It's not equal to x29, It also goes to the incorrect processing branch

Or it can be understood as ： if  (x7 < 0)  &&  (x6 + x7 >= x6)  ||  (x7 >= 0)  &&  (x6 + x7 < x6) Is an incorrect processing branch

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