Verilog grammar basics HDL Bits training 07

Circuits:Combinational Logic:Multiplexers

一、2-to-1 multiplexer

设计一个二选一多路器

• RTL代码

module top_module( 
    input a, b, sel,
    output out ); 
    
    always @(*)
        case(sel)
            1'b0 : out = a;
            1'b1 : out = b;
        endcase

endmodule

• 仿真波形图
  

二、2-to-1 bus multiplexer

• RTL代码

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    
    always @(*)
        case(sel)
            1'b0 : out = a;
            1'b1 : out = b;
        endcase

endmodule

• 仿真波形图
  

三、9-to-1 multiplexer

Design a sixteen-to-one multiplexer

• RTL代码

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    
    always @(*)
        case(sel)
            4'b0000 : out = a;
            4'b0001 : out = b;
            4'b0010 : out = c;
            4'b0011 : out = d;
            4'b0100 : out = e;
            4'b0101 : out = f;
            4'b0110 : out = g;
            4'b0111 : out = h;
            4'b1000 : out = i;
            default : out = 16'hffff;
        endcase

endmodule

• 仿真波形图
  

四、256-to-1 multiplexer

256so many options,case就不能用了,Use variable indexing to accomplish the task,Also pay attention to the bit width of variables and vectors when using them

• RTL代码

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );

    assign out = in[sel];

endmodule

五、256-to-1 4-bit multiplexer

Use the bit stitching method to make choices more flexible

• RTL代码

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    
    assign out = {
    in[sel*4+3] , in[sel*4+2] , in[sel*4+1] , in[sel*4]};
    
endmodule