Verilog daily question (vl28 plus and minus counter)

Title Description

Please write a decimal counter module , When mode The signal is 1, The counter output signal is incremented , When mode The signal is 0, The counter output signal decreases . Every time I arrive 0, Give an indication signal zero.
The interface signal diagram of the module is as follows ：

 

  There is a problem with the waveform here , When the first rising edge comes , Already started adding one , there num It's an intermediate counter ,number Being assigned will slow down , But it can't be seen ... The question of niuke.com is really , still HDLbits Have fun .

After considering this , It's easy . The specific problem-solving process is as follows ：

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
    reg [3:0] num; // Make a statement reg Variables as intermediate counts 
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) num <= 0 ;
        else if(num==9&&mode==1) num<=0; // Want to consider num=9 Continue to increase time-varying 0 The situation of 
        else if(num==0&&mode==0) num<=9; // Want to consider num=0 Continue to reduce time variation 9 The situation of 
        else if(mode==1) num<=num+1;    //mode Control addition and subtraction 
        else if(mode==0) num<=num-1;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) number <= 0; // take num Assign a value to number
        else number <= num;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) zero = 0;
        else if(num==0) zero <= 1;
        else zero <= 0;
    end

endmodule

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