A 64 bit 8-stage pipelined adder based on FPGA

Use verilog Realization ,qurartus Create engineering and simulation ;
Principle that
64 position 8 Stage pipeline adder , That is, will 64 The position is divided into 8 individual 8 Bit operation , The final will be 8 individual 8 The result of bit operation is added to get the final sum and carry . use 8 Stage pipeline performs addition operation , Then from the first clock when two addends are input for the first time , You need the 8 The sum of clock cycles is output , Then input the addend continuously , Zehe also keeps outputting , As shown in the figure below ：

8 The stage pipeline needs to split the addition operation into 8 Two clock cycles to complete , Each clock cycle requires the sum of the previous calculations 、 The addends that have not been calculated are cached , thus , For example 1 individual 8 The sum of bits needs to be cached 7 Time , The first 2 individual 8 The sum of bits needs to be cached 6 Time , And so on . meanwhile , Also cache the addends that have not been calculated , such as [63:56] This 8 Bit requires caching 7 Time ,[55:48]  This 8 Bit requires caching 6 Time .

The first 1 Clock cycles ： Computation first 1 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Addends not calculated
The first 2 Clock cycles ： Computation first 2 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Addends not calculated
The first 3 Clock cycles ： Computation first 3 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Addends not calculated
The first 4 Clock cycles ： Computation first 4 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Addends not calculated
The first 5 Clock cycles ： Computation first 5 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Addends not calculated
The first 6 Clock cycles ： Computation first 6 individual 8 The sum of bits , And add the carry of the previous . Cache the previous sum 、 Not calculated