当前位置：网站首页>Complex floating point division of vivado IP core floating point
Complex floating point division of vivado IP core floating point
2022-07-29 06:39:00 【Doze in the wind】
Vivado IP Core complex floating point division Floating-point
Catalog
One 、 Example of division of complex floating point numbers
Two 、Floating-point IP Core configuration steps
Preface
With the continuous development of manufacturing technology , Field programmable logic gate array （FPGA） More and more integration , More and more applications , Among them, some mathematical processing classes must be used when processing digital signals IP nucleus . Recently, research on Spatial Adaptive Anti-jamming Technology is under way FPGA Hardware implementation , Some of them are inevitably used IP nucleus , Today I will introduce how to use vivado In the middle of Floating-point This IP Kernel Implementation Division of complex floating point numbers , I hope it can help you in your study .
Tips ： The following is the main body of this article , All are original by the author , It's not easy to write an article , I hope you will attach a link to this article when reprinting .
One 、 Example of division of complex floating point numbers
In order to facilitate the analysis of the results of the later simulation , Here we will give an example of the division of complex floating-point numbers , The following example is directly used for simulation , To verify whether the simulation results are correct .
example： Set floating point number a=32'h4057AE14+j32'h400F5C29, namely a=3.37+j2.24, Floating point numbers b=32'h3FE51EB8+j32'hC039999A, namely b=1.79-j2.9, be a/b=32'hBD236E2F+32'h3F97E5C9, namely a/b=-0.0399+j1.1867, Note that the result retains only four decimal places .
Two 、Floating-point IP Core configuration steps
About Floating-point IP How to configure the addition, subtraction, multiplication and division of the kernel has been explained in the previous articles , Students who won't read my previous article , No more details here .
3、 ... and 、 The whole idea
According to the formula 
, Let's use six parallel multipliers to calculate ac,bd,ad,bc,cc,dd Result , Then a subtractor and two adders are used to calculate in parallel bc-ad and ac+bd、cc+dd, Finally, two dividers are used to calculate in parallel 
and 
that will do . In my IP Core configuration , Multiplier IP The nuclear delay is 8 A clock , Adders and subtracters IP The nuclear delay is 11 A clock , A divider IP The nuclear delay is 28 A clock , To make sure that there is no risk , In my code , For data valid signals Valid Gave oneortwo more clocks . In the whole top-level code , Count cnt Particularly important , Many intermediate variables change depending on cnt The numerical . There are also many comments in the code , This design idea is not difficult , I believe you can understand .
Four 、 Simulation
1. Top level code
Build a top-level module , Name it float_complex_div.
The code is as follows ：
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/26 12:30:21
// Design Name:
// Module Name: float_complex_div
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
// Calculation formula ： (a+bi)/(c+di)=( ac+bd+(bc-ad)i )/(c^2+b^2)
module float_complex_div(
input clk, // Input clock signal
input rst_n, // Input reset signal
input start, // Input the start signal
input [31:0] re_a, // Enter the divisor a The real part of
input [31:0] im_a, // Enter the divisor a The imaginary part of
input [31:0] re_b, // Enter divisor b The real part of
input [31:0] im_b, // Enter divisor b The imaginary part of
output reg over, // Output calculation completion signal
output reg [31:0] re_res, // Output the real part of the calculation result
output reg [31:0] im_res // Output the imaginary part of the calculation result
);
//reg define
reg [5:0] cnt; // Process count flag
reg valid1; // Multiply by valid signal
reg valid2; // Plus or minus effective signal
reg valid3; // Divide effective signal
//wire define
wire [31:0] result1; // result 1
wire [31:0] result2; // result 2
wire [31:0] result3; // result 3
wire [31:0] result4; // result 4
wire [31:0] result5; // result 5
wire [31:0] result6; // result 6
wire [31:0] result7; // result 7
wire [31:0] result8; // result 8
wire [31:0] result9; // result 9
wire [31:0] result10; // result 10
wire [31:0] result11; // result 11
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt<=0;
else if(start==1)
begin
if(cnt<6'd56)
cnt<=cnt+1;
else
cnt<=0;
end
else if(start==0)
cnt<=0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
valid1<=0;
else if(6'd0<cnt<=6'd9)
valid1<=1;
else
valid1<=0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
valid2<=0;
else if(6'd12<cnt<=6'd24)
valid2<=1;
else
valid2<=0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
valid3<=0;
else if(6'd24<cnt<=6'd53)
valid3<=1;
else
valid3<=0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin over<=0;re_res<=0;im_res<=0; end
else if(cnt==6'd55)
begin over<=1;re_res<=result10;im_res<=result11; end
else
begin over<=0;re_res<=0;im_res<=0; end
float_mul_ip u1_float_mul_ip( // Multiplier 1 Calculation ac
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(re_a),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(re_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result1)
);
float_mul_ip u2_float_mul_ip( // Multiplier 2 Calculation bd
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(im_a),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(im_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result2)
);
float_mul_ip u3_float_mul_ip( // Multiplier 3 Calculation ad
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(re_a),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(im_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result3)
);
float_mul_ip u4_float_mul_ip( // Multiplier 4 Calculation bc
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(im_a),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(re_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result4)
);
float_mul_ip u5_float_mul_ip( // Multiplier 5 Calculation c*c
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(re_b),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(re_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result5)
);
float_mul_ip u6_float_mul_ip( // Multiplier 6 Calculation d*d
.aclk(clk),
.s_axis_a_tvalid(valid1),
.s_axis_a_tdata(im_b),
.s_axis_b_tvalid(valid1),
.s_axis_b_tdata(im_b),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result6)
);
float_sub_ip u1_float_sub_ip( // Subtracter Calculation bc-ad
.aclk(clk),
.s_axis_a_tvalid(valid2),
.s_axis_a_tdata(result4),
.s_axis_b_tvalid(valid2),
.s_axis_b_tdata(result3),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result7)
);
float_add_ip u1_float_add_ip( // adder 1 Calculation ac+bd
.aclk(clk),
.s_axis_a_tvalid(valid2),
.s_axis_a_tdata(result1),
.s_axis_b_tvalid(valid2),
.s_axis_b_tdata(result2),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result8)
);
float_add_ip u2_float_add_ip( // adder 2 Calculation cc+dd
.aclk(clk),
.s_axis_a_tvalid(valid2),
.s_axis_a_tdata(result5),
.s_axis_b_tvalid(valid2),
.s_axis_b_tdata(result6),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result9)
);
float_div_ip u1_float_div_ip( // A divider 1 Calculation (ac+bd)/(cc+dd)
.aclk(clk),
.s_axis_a_tvalid(valid3),
.s_axis_a_tdata(result8),
.s_axis_b_tvalid(valid3),
.s_axis_b_tdata(result9),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result10)
);
float_div_ip u2_float_div_ip( // A divider 2 Calculation (bc-ad)/(cc+dd)
.aclk(clk),
.s_axis_a_tvalid(valid3),
.s_axis_a_tdata(result7),
.s_axis_b_tvalid(valid3),
.s_axis_b_tdata(result9),
.m_axis_result_tvalid(),
.m_axis_result_tdata(result11)
);
endmodule
2. Simulation code
Build a simulation module , Name it float_complex_div_tb, Used to simulate top-level modules .
The code is as follows ：
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/26 13:32:30
// Design Name:
// Module Name: float_complex_div_tb
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
module float_complex_div_tb();
reg clk; // Input clock signal
reg rst_n; // Input reset signal
reg start; // Input the start signal
reg [31:0] re_a; // Input factor a The real part of
reg [31:0] im_a; // Input factor a The imaginary part of
reg [31:0] re_b; // Input factor b The real part of
reg [31:0] im_b; // Input factor b The imaginary part of
wire over; // Output calculation completion signal
wire [31:0] re_res; // Output the real part of the calculation result
wire [31:0] im_res; // Output the imaginary part of the calculation result
float_complex_div u1_float_complex_div( // Instantiate top-level modules
.clk(clk),
.rst_n(rst_n),
.start(start),
.re_a(re_a),
.im_a(im_a),
.re_b(re_b),
.im_b(im_b),
.over(over),
.re_res(re_res),
.im_res(im_res)
);
always #5 clk=~clk;
initial begin
clk=1'b0;rst_n=1'b1;start=1'b0;
#5; rst_n=1'b0;
#10; rst_n=1'b1;
start=1'b1;
re_a=32'h4057ae14;
im_a=32'h400f5c29;
re_b=32'h3fe51eb8;
im_b=32'hc039999a;
#560 start=1'b0;
end
endmodule5、 ... and 、 Analysis of simulation results
The simulation results are shown in the figure 1 Shown , Compare the examples of division of complex floating-point numbers listed above , It can be seen that this module successfully realizes the division of complex floating-point numbers . The result is 32'hBD23891A+j32'h3F97E634, namely -0.039925672+j1.1867127, If you keep four decimal places, it will be -0.0399+j1.1867, This is consistent with the example introduced at the beginning of this article .
summary
This introduces the division of complex floating-point numbers .
边栏推荐
- Explain the difference between FIR filter and IIR filter in detail
- 虹科Automation softPLC | 虹科KPA MoDK运行环境与搭建步骤(2)——MoDK运行环境搭建
- Advanced socket programming (options and control information)
- RAW高级套接口实验
- Solve the error that the simulation output is STX under the frequency division module Modelsim
- The performance and viewing methods of websites attacked by DDoS
- 摊余成本最牛例子
- 虹科方案 | 在数字化的变电站中低成本实现无缝集成的独特解决方案
- Design of IIR filter based on FPGA
- Verilog中for语句的使用
猜你喜欢
On defect description style
自动化测试的生命周期是什么？
Vivado IP核之浮点数乘除法 Floating-point
虹科分享 | 带您全面认识“CAN总线错误”（一）——CAN总线错误与错误帧
day09_ Static & Final & code block & abstract class & Interface & internal class
Design and simulation code of 4-bit subtracter based on FPGA
Vivado IP核之浮点数加减法 Floating-point
Arrays & object & System & Math & random & Packaging
What is the lifecycle of automated testing?
MerkleTree 构建QT实现UI
随机推荐
Merkle tree existential function modified for the first time
FPGA里两个数的大小直接进行比较就可以吗？
多线程服务器编程
虹科教您 | 想进入TSN领域？虹科教您如何搭建TSN测试系统
虹科案例 | PAC：一种整合了softPLC控制逻辑、HMI和其他服务功能的集成控制解决方案
day17_集合下
网站被挂马的解决方案
day03_ 2_ task
3、 Wide area communication network
Network Security Learning (II)
四、 局域网和城域网
多路IO用法
4、 LAN and man
什么是撞库及撞库攻击的基本原理
Merkletree builds QT implementation UI
Design and simulation code of 4-bit subtracter based on FPGA
Multiple IO usage
DDoS details
Vivado IP核之RAM Block Memery Generator
day04_数组