set_ clock_ groups

set_clock_groups There are three options ：-asynchronous,-logically_exclusive,-physically_exclusive, You must select one of them when using .

1、-asynchronous

Asynchronous clock does not need to be done timing check , The sample is shown in figure 1, If C1 and C2 these two items. clock It's asynchronous , Generally speaking, you don't need check This article path Of , At this point, you can use the following command to tell the tool ： 

set_clock_group -asynchronous  -group C1 -group C2

chart 1 

2、logical exclusive

Logical mutual exclusion , If there are two in a circuit clock, They don't exist timing check, for example , There is a choice of signal control of the two clock, Pictured 2, These two clock Yes, it should be declared as logical exclusive Of , The order is as follows ： 

create_clock -period 10 -name C1 -waveform {0 5} [get_ports C1] 
create_clock -period 12 -name C2 -waveform {0 6} [get_ports C2] 
set_clock_groups -logically_exclusive -group C1 -group C2

chart 2 

This happens in addition to using set_clock_groups You can also use set_false_path.

set_false_path-from [get_clocks C1] -to [get_clocks C2]
set_false_path-from [get_clocks C2] -to [get_clocks C1]

3、physical exclusive

Mutual exclusion at the physical level , For example, it is defined in the same port/pin Differences on clock, Pictured 3. here C1 clock（F3） and C2 clock （F4） between timing check, however F1->F2 Between timing check, because clock path after MUX The choice of , So it can only be C1->C1 or C2->C2, There can't be C1->C2 or C2->C1, At this time, you need to MUX Then define two generate clock, And then use set_clock_groups -physically_exclusive The two one. generate clock Set mutual exclusion at the physical level .

create_clock -period 10 -name C1 -waveform {0 5  } [get_ports C1] 
create_clock -period 20 -name C2 -waveform {0 12} [get_ports C2]  
create_generated_clock -name GC1 -divide_by 1 \
        -source [get_pins mux1/A] [get_pins mux1/Z] -combinational 
create_generated_clock -name GC2 -divide_by 1 \
        -source [get_pins mux1/B] [get_pins mux1/Z] -combinational -add  
set_clock_groups -physically_exclusive -group GC1 -group GC2

chart 3 

4、SI analysis

Doing it SI When analyzing -physical exclusive No analysis group Crosstalk between ,-logical exclusive Only analyze timing window Overlapping parts crosstalk,-asynchronous Think timing window infinity （infinite window：timing window Completely interlaced , Do it at any time SI analysis ）, At this time SI It has a big impact . This part can refer to PT Of user guide.