SystemVerilog structure (II)

Digital hardware modeling SystemVerilog- Structure （ Two ）

Structure

Structs are used to combine multiple variables under a common name . Designs usually have logical signal groups , For example, the control signal of the bus protocol , Or signals used in the state controller . The struct provides a way to bundle these related variables together . All variables in the structure can be assigned a single value , Or each variable can be assigned a value separately . A structure package can be copied to another structure with the same definition , And through the module port 、 Task or function in and out .

Structure replication

One custom structure can be copied to another , As long as these two structures are declared from the same custom structure definition . The following example uses the structure definitions and declarations shown in the previous section .

Anonymous structures cannot be copied as a whole , But you can copy one member at a time ：

Compressed and uncompressed structures

By default , The structure will be uncompressed . This means that members of the structure are treated as independent variables or constants , And grouped together under a common name .SystemVerilog It does not specify how software tools should store members of uncompressed structures . Different software tools have different storage distribution for structures .

By using keywords packed, Explicitly declare the structure as a compressed structure .

The compressed structure stores all members of the structure as continuous bits in the same form as the vector . The first member of the structure is the leftmost field of the vector . The rightmost bit of the last member in the structure is the least significant bit of the vector , The number is bit 0. Pictured 4-2 Shown .

chart 4-2： Compressed structure stored as vector

All members of a compressed structure must be integer values . Integer values are values that can be expressed as vectors , for example byte、int And use bit or logic Vector created by type . If any member of the structure cannot be expressed as a vector , Then the structure cannot be compressed . This means that compressed structures cannot contain real or short real variables 、 Incompressible structure 、 An uncompressed union or an uncompressed array .

Reference compressed structure and structure members . Compressed structures can be copied , Or assign a list of structural expression values , The method is the same as that of an uncompressed structure . Members of compressed structures can be referenced by member names , The method is the same as that of an uncompressed structure .

The compressed structure can also be regarded as a vector . therefore , In addition to structure allocation , Vector values can also be assigned to compressed structures

Vector assignment is legal , Because the structure members on the left of the assignment have been compressed together , Form a continuous set of bits , In the same way as vectors . Because the compressed structure is stored as a continuous set of bits , Therefore, it is also legal to perform vector operations on compressed structures , Including bit selection and partial selection . The following two assignments will be assigned to data_word Of tag member ：

Mathematical operations that can be performed on vectors 、 Logical operations and any other operations can also be performed on compressed structures .

Signed compressed structure . Compressed structure can be used signed and unsigned Keyword declaration . When used as a vector in operations or relational operations , These modifiers will affect the recognition method of the whole structure . They will not affect the way the structure members are identified . Each member of the structure is considered to be signed or unsigned , It depends on the type declaration of the member . The partial selection of compressed structure is unsigned , Same as partial selection of vector .

Pass the structure through the port

Custom structures can be passed through the ports of modules and interfaces , The structure must first use typedef Define user-defined data types , Then it is allowed to declare the port of the module or interface as the structure type .

Uncompressed structures must be custom structures , Can the structure be passed through the port . The connection with the port must be a structure exactly the same as the port type . in other words , The port and the connections on both sides of the port must be from the same typedef Definition statement . This limitation applies only to uncompressed structures . The compressed structure through the module port is regarded as a vector . The external connection of the port can be the same type of compressed structure , It can also be any type of vector .

By declaring task or function parameters as struct types , Custom structures can also be passed to tasks or functions as parameters .

When calling a task or function , If the task or function has an uncompressed structure as a formal parameter menu , Then a structure of exactly the same type must be passed to the task or function . The formal parameters of compressed structure are regarded as vectors , Can be passed to any type of vector .

Conventional Verilog And the structure

The original Verilog Language does not have a convenient mechanism to collect common signals into a group . In traditional Verilog Style model , Engineers must use a special grouping method , For example, naming conventions , Each signal in one group starts or ends with a set of common characters . The original Verilog Language also cannot pass signal sets through module ports or tasks and functions , Each signal must be transmitted through a separate port or parameter .

In primitive Verilog Adding structures to a language is a powerful RTL Modeling construction , vice versa . It provides a more concise 、 More intuitive 、 More reusable complex model function modeling method . The custom structure defined in the package can be reused in multiple modules , It can also be used for verification RTL The model is reused in the validation test bench .

Comprehensive guidance

Both uncompressed and compressed structures can be integrated . The integrated tool supports the structure to pass through the module port , It also supports passing to tasks and functions as input or output , It also supports assigning values to structures using a list of member names and values .

Synthetic compilers may optimize uncompressed structures better than compressed structures . Uncompressed structures allow software tools to determine the best way to store or implement each structure member , The compressed structure determines how to organize each member .

SystemVerilog- Structure （ One ）