[FPGA] joint simulation of vivado and Modelsim

Two 、 Problems encountered

1. A wrong ：

# ** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

Solution ： modify timescale 10 ns / 1 ns, Usually timescale A /B, One time unit away , namely $10^3$
2. Error 2

Actual expression (function cal1 "SHL") of formal "Code_Fcw" 1is not globally static.

Solution ： The corresponding VHDL Change the document to VHDL-2008
modesim The operation method in is ：
Select the file and right-click , choice ->properties. Click on the page that pops up VHDL. As shown in the figure below
choice use 1076-2008 that will do .

vivado How to operate in the process ：
open vivado in tools Under the Property editor （property Editor）, And then in FILE_TYPE Choose from VHDL 2008 that will do .

3、 ... and 、 Reference material ：

【1】Vivado 2019.01 And Modelsim 10.07 Joint simulation of
【2】vidado 2019.2 And modelsim2019.2 Installation 、 Crack 、 Joint simulation configuration
【3】Mentor Graphics ModelSim 2019.2 64 Bit English installation tutorial
【4】vivado And modelsim Joint simulation of
【5】vivado2018.3 And modelsim Co simulation
【6】modelsimSE-64 10.6 Install and connect with vivado Joint tutorial