[2023 Fudan Microelectronics written examination questions in advance] ~ questions and reference answers

0. the front

This written examination can only be described in one word — miscellaneous . How dare you believe it ？ There are all kinds of questions in a set of papers , Not only have IC Design direction , also IC Verify directional , The most terrible thing is that there is back-end knowledge , It can be described as the selection of all-round talents , It's really a drunken man's intention, not wine ！

There are three parts in the exam paper ： Base part 、 Optional part 、 Verification part .

There are ten questions in the basic part ; It seems that the optional part is also ten questions ; Five questions in the verification part .

The following is a specific topic , Just memories , Ha ha ha ！！！

1. Base part

The first question is

problem

What is? RTL Class design ？

answer

RTL（Register-Transfer-Level）, It refers to a way to describe the data flow of a circuit by using the description mode of register . It can be integrated , Therefore, its programming style should be code recognizable by comprehensive tools , Net list can be generated directly through comprehensive tools . It is the upper level of behavior level description , Behavior level description focuses more on algorithms , Generally, the realization and integrability of the circuit are not considered , Only define the input-output relationship , It is more abstract than behavior level description .

Knowledge development

RTL What is the difference between level and gate level ？

RTL It describes the function you want to achieve with hardware description language , Gate level uses specific logic units （ Rely on the manufacturer's Library ） To realize your function , Gate level can finally be processed into actual hardware in semiconductor factory . All in all ,RTL And gate level are different stages of design and implementation ,RTL After logical synthesis , Get the door level .

RTL The description can be expressed as a finite state machine , Or a more general sequential state machine that can transfer registers on the boundary of a predetermined clock cycle , Usually VHDL/verilog Describe in two languages .

To be specific , Soft core can be integrated HDL describe , Hard core is chip layout , Solid core is gate level HDL describe .

The second question is

problem

What is competition ？ What is adventure ？ How to eliminate ？

answer

Before written , Portal

Third question

problem

Design flow in integrated circuit ？ Used in all links EDA Tools ？

answer

Just wrote an article , You can see , Portal

Fourth question

problem

latch and DFF The difference between ？

answer

Before written , Portal

Fifth question

problem

The difference between blocking assignment and non blocking assignment ？

answer

Before written , Portal

Sixth question

problem

DMA The advantages of ？

answer

Portal

Question seven

problem

Gave a circuit diagram , Let's talk about how to test a signal for errors ？

answer

This can't be written , Let's talk about my thoughts , I think we have to write the logical expression , After simplification , Give other signals all valid , Just observe the signal that needs to be detected .

The eighth question

problem

Whether the two-level synchronization code is correct ？

answer

Code question , Just brush more questions , Portal

Question 9

problem

Code question ： The width of the detection input signal is greater than one clock clock cycle ？

answer

At present, I haven't thought of a good method for this problem , Update later ！

Question 10

problem

use CMOS Telephone circuit diagram ？

answer

This question is not within my ability , Ha ha ha , Learn first and then update ！

2. Optional part

This part is the last one , Not impressive , Because the time is short , There is no time to finish reading .

3. Verification part

The first question is

problem

What is the coverage of validation ？ What's the point ？

answer

Portal

The second question is

problem

The verification platform has several parts ？UVM What are the components ？ What is factory mode ？ What are the key signals ？

answer

Portal

Third question

problem

Simulation cannot continue ,stuck In a bit , What is the reason ？

answer

I said it in combination with my personal situation

Fourth question

problem

I forgot this ？

answer

Fifth question

problem

I didn't remember this , Time is too urgent ？

answer

reference

About RTL And gate level

Statement

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I mainly record the learning process , For myself to review , Then it is to provide reference for future generations , No joy, no spray. ！！！

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