[introduction to UVM== > episode_9] ~ register model, integration of register model, general methods of register model, application scenarios of register model

1. Register model

1.1 summary

1.2 model

1.3 Centralized management

1.4 uvm_reg

1.4.1 MCDF Register model

1.5 Register modeling

1.5.1 Model usage process

2. Register model integration

2.1 Bus UVC

2.1.1 What is? UVC？

UVC The full name is UVM Component, It is often the lowest level component used in our build environment , Although it is “ Small ”, But it's very important , Many module level validations even SOC The same... Will be used for validation UVC, Pull one hair and move the whole body .

2.1.2 What is? VIP？

there VIP It's not in everyone's life VIP ah ！ Here means Verification IP,VIP A much wider range , More for third parties （ There are also self-developed enterprises VIP）, It may be more than just a uvm The components of , May be a pure sv Object collection for , It may also be some verilog Of model, therefore uvc yes vip A nonempty proper subset of .

2.1.3 Realization

2.1.4 Code parsing

2.2 MCDF Register design code

2.3 Adapter

2.3.1 summary

2.3.1.1 nothing predictor

2.3.1.2 Yes predictor

2.3.2 Realization

2.3.3 analysis

2.3.4 Integrate

2.3.4.1 Code implementation

2.3.5 access

2.3.5.1 Front door access

2.3.5.2 Illustrate with examples

2.3.5.3 Back door access

2.3.5.4 Illustrate with examples

2.3.5.5 A comparison of the two

2.3.5.6 Hybrid applications

3. The general method of register model

3.1 mirror、desired and actual value

3.2 prediction The classification of

3.2.1 Automatic prediction

3.2.2 Show forecast

3.3 Access method

3.4 mem And reg The connections and differences between

3.5 The built-in （build-in）sequences

4. Application scenarios of register model

4.1 summary

4.2 Register check

4.3 Overview of functional coverage

4.3.1 Illustrate with examples