[turn to] FPGA interview questions

1： What is synchronous logic and asynchronous logic ？
Synchronization logic is that there is a fixed causal relationship between clocks . Asynchronous logic is that there is no fixed causal relationship between the clocks . The answer should be consistent with the above question
〔 Add 〕： Characteristics of synchronous sequential logic circuit ： The clock ends of each trigger are all connected together , And connected to the clock end of the system , Only when the clock pulse comes , The state of the circuit can be changed . The changed state will be maintained until the arrival of the next clock pulse , At this time, regardless of external input x Is there any change , Each state in the state table is stable .   
Characteristics of asynchronous sequential logic circuits ： In addition to using a trigger with a clock in the circuit , Flip flops and delay elements without clocks can also be used as storage elements , There is no uniform clock in the circuit , The change of circuit state is directly caused by the change of external input .

2： The difference between synchronous circuit and asynchronous circuit ：
Synchronous circuit ： The clock input terminals of all flip flops in the storage circuit are connected to the same clock pulse source , Therefore, the state changes of all flip flops are synchronized with the added clock pulse signal .
Asynchronous circuits ： There is no uniform clock for the circuit , The clock input of some flip flops is connected to the clock pulse source , This has the state changes of these flip flops synchronized with the clock pulse , The state changes of other flip flops are not synchronized with the clock pulse .

3： The essence of timing design ：
    The difficulty of circuit design lies in timing design , The essence of timing design is to meet the establishment of each trigger / Requirements for holding time .

4： Establish the concept of time and hold time ？
    Set up time ： The trigger is before the rising edge of the clock comes , The time that the data at its data input must remain unchanged .
    Retention time ： The trigger comes after the rising edge of the clock , The time that the data at its data input must remain unchanged .

Regardless of the clock skew,D2 The creation time of cannot be greater than （ Clock cycle T - D1 The latest arrival time of data T1max+T2max）; The holding time cannot be longer than （D1 Fastest data arrival time T1min+T2min）; otherwise D2 The data will enter metastable state and propagate to the backward stage circuit
（ Adventure can also spread ）

5： Why do triggers need to meet the set-up time and hold time ？
Because the formation of internal data of trigger takes a certain time , If you don't meet the setup and hold time , The trigger will enter metastable state , After entering the metastable state, the output of the trigger will be unstable , stay 0 and 1 Change between , At this time A recovery time is required , Its output can be stable , But the stable value is not necessarily your input value . This is why two-stage flip flops are used to synchronize asynchronous input signals . Doing so prevents asynchronous input The signal may not meet the establishment and holding time for the current level clock, so that the metastable state generated by the current level trigger is propagated to the following logic , Lead to the propagation of metastable state .
（ Easier to understand ） Another way to understand ： The setup time is needed because of the trigger's D Segment is like a latch receiving data , In order to set the state of the front door stably, it needs a period of stabilization time ; You need to hold time because after the edge of the clock comes , The trigger should feedback the stored state , It takes time to transfer from the rear gate to the front gate .

6： What is metastable ？ Why can two-stage flip flops prevent metastable propagation ？
This is also a problem of asynchronous circuit synchronization , For details, please refer to 《EDACN Technology Monthly 20050401》.
Metastable state means that the trigger cannot reach an identifiable state within a specified period of time . A circuit that uses two-stage triggers to synchronize asynchronous circuits is actually called “ One step positioner ”, He can only be used to asynchronize one Signal synchronization . The principle that two-stage trigger can prevent metastable propagation ： Suppose that the input of the first stage trigger does not meet its establishment and holding time , Its output data after the arrival of the first pulse edge is metastable , Then I'll A pulse comes along before , The output metastable data must be stable after a period of recovery time , Moreover, the stable data must meet the establishment time of the second level trigger , If you are satisfied , At the next pulse along to when , The second stage trigger will not be metastable , Because the data at its input meets its establishment and holding time . Conditions for synchronizer validity ： Recovery time after the first stage trigger enters metastable state + The setup time of the second level trigger < = Clock cycle .
To be more exact , The input pulse width must be greater than the sum of the synchronization clock cycle and the holding time required by the first stage trigger . The safest pulse width is twice the synchronous clock cycle . therefore , Such a synchronous circuit is more effective for asynchronous signals from the slower clock domain to enter the faster clock domain , For entering a slower clock domain , It doesn't work .

7： The maximum speed of the system is calculated （ Fastest clock frequency ） And pipeline design ideas ：
The speed of the synchronization circuit refers to the speed of the synchronization system clock , The faster the synchronization clock , The shorter the time interval between circuit processing data , The more data a circuit can process per unit time . hypothesis Tco Is the input data of the trigger The delay time from the time when the clock is put into the trigger to the time when the data reaches the output of the trigger ;Tdelay Is the delay of combinatorial logic ;Tsetup yes Ｄ Trigger setup time . Suppose the data has been clocked in D Trigger device , Then the data reaches the first trigger Ｑ The delay time required at the output is Tco, The delay time after combinational logic is Tdelay, Then we get to the second trigger Ｄ End , Hope that the clock will be on the The two triggers are steadily pushed into the trigger again , The clock delay must be greater than Tco＋Tdelay＋Tsetup, That is, the minimum clock cycle Tmin =Tco＋Tdelay＋Tsetup, The fastest clock frequency Fmax =1/Tmin.FPGA Developing software also calculates the maximum running speed of the system through this method Fmax. because Tco and Tsetup It is determined by the specific device process , Therefore, when designing the circuit, only It can change the delay time of combinatorial logic Tdelay, Therefore, shortening the delay time of combinational logic between triggers is the key to improve the speed of synchronous circuit . Because the general synchronization circuit is larger than the first level latch , But to make electricity Road stability work , The clock cycle must meet the maximum delay requirements . Therefore, only the longest delay path can be shortened , To improve the working frequency of the circuit . Larger combinational logic can be decomposed into smaller N block , Flatten by appropriate means Equally distributed combinatorial logic , Then insert a trigger in the middle , And use the same clock as the original trigger , You can avoid excessive delay between two triggers , Eliminate speed bottlenecks , This can improve the operation of the circuit frequency . That's what's called " Assembly line " The basic design idea of technology , That is, the speed limited part of the original design is realized by one clock cycle , After using pipeline technology to insert trigger , You can use N Clock cycles , So the system The speed of work can be accelerated , Increased throughput . Be careful , Pipeline design will add delay to the original data path , In addition, the hardware area will be slightly increased .

8： The concept and basic strategy of temporal constraints ？
Temporal constraints mainly include periodic constraints , Offset constraint , There are three kinds of static timing path constraints . By adding timing constraints, the generic cabling tool can adjust the mapping and layout , The design meets the timing requirements .
The general strategy for adding temporal constraints is to add global constraints first , Then add special constraints for fast and slow exception paths . When adding a global constraint , First define all the clocks of the design , The synchronization elements in each clock domain are grouped , Add a periodic constraint to the group , Then on FPGA/CPLD Input and output PAD Add an offset constraint 、 For all combinatorial logic PAD TO PAD Add constraints to the path . When adding special constraints , First, the paths between groups are constrained , Then constrain fast 、 Slow exception paths and multi cycle paths , And other special paths .

9： Add the role of constraints ？
    effect ：1： Improve the working frequency of the design （ Reduced logic and wiring delays ）;2： Get the correct timing analysis report ;（ The static timing analysis tool takes constraints as the criteria to judge whether the timing meets the design requirements , Therefore, designers are required to input constraints correctly , So that the static timing analysis tool can correctly output timing reports ）3： Appoint FPGA/CPLD Electrical standards and pin locations for .

10：FPGA The direction of the Design Engineer ：
SOPC, High speed serial I/O, low power consumption , reliability , Testability and optimization of design verification process . With the improvement of chip technology , Chip capacity 、 Integration is increasing ,FPGA The design is also moving towards high speed 、 Height set become 、 low power consumption 、 high reliability 、 Highly measurable 、 Verifiability development . Chip testable 、 Verifiable , It is becoming a necessary condition for complex design , Try to find out before loading bug, Will find bug Ahead of time , This is why some companies have made great efforts to design simulation platforms . In addition, with the improvement of the board functions 、 Cost pressure , Low power consumption is also gradually entering FPGA The designer's scope of consideration , Complete the same function , Consider how to minimize the power consumption of the chip , It is said that altera、xilinx They are sorting out documents on how to reduce power consumption according to their own chip characteristics . High speed serial IO Application , It also enriches FPGA Application scope of around , like xilinx Of v2pro The high-speed link in is also gradually applied . All in all , knowledge has no limit , When you master a certain concept 、 After method , It's time to start thinking about FPGA Other problems .

11： How to synchronize multi bit asynchronous signals ？
For asynchronous signals with one bit, you can use “ One synchronizer for synchronization ”, For multi bit asynchronous signals , The following methods can be used ：1： The method of holding register and handshake signal can be adopted （ More data , control , Address ）;2： Special application circuit structure , It varies according to the application ;3： asynchronous FIFO.（ The most commonly used cache unit is SDRAM）

12：FPGA and CPLD The difference between ？
FPGA It's programmable ASIC.  

ASIC: ASIC , It is a special purpose oriented circuit , Specially designed and manufactured for one user . According to the specific requirements of a user , It can be developed at low cost , Full customization of short lead time supply , Semi custom integrated circuit . And gate array ASIC(ApplicaTIon Specific IC) comparison , They also have the advantages of short design and development cycle 、 Low design and manufacturing cost 、 Development tools are advanced 、 Standard products do not need to be tested 、 It has the advantages of stable quality and real-time on-line inspection .

CPLD FPGA
internal structure Product－term Look－up Table
Program storage Inside EEPROM SRAM, plugin EEPROM
The resource type The resources of combinational circuits are abundant Rich trigger resources
Integration low high
Use occasion Complete the control logic Can complete more complex algorithms
Speed slow fast
Other resources － PLL、RAM And multipliers
confidentiality It can be encrypted Generally, it cannot be kept confidential

CPLD
With altraMAX7000 such PLD For example , It can be divided into three parts ： Macro unit （Marocell), Programmable wiring （PIA) and I/O Control block . Macro cells are PLD Basic structure , It is used to realize basic logic functions . Programmable wiring is responsible for signal transmission , Connect all macro units .I/O The control block is responsible for controlling the electrical characteristics of the input and output , For example, open collector output can be set , Swing rate control , Three state output, etc .
This is based on the product term （ It's actually an and or array ） Of PLD It's basically all about EEPROM and Flash Made by craft , It can work as soon as it is powered on , No other chips are required . The routing method is global , So the delay is predictable .CPLD Suitable for logic design .

FPGA
FPGA be based on LUT,LUT It's essentially one RAM, every last LUT It can be seen as a being 4 Bit address line 16x1 Of RAM. That's why FPGA Need an external rom Power on configuration .
With xilinx Of Spartan-II For example , It mainly includes CLBs,I/O block ,RAM Block and programmable wiring . stay spartan-II in , One CLB Include 2 individual Slices, Every slices It includes two LUT, Two triggers and related logic . Slices It can be seen as SpartanII The most basic structure of implementation logic .
FPGA The manufacturing process of determines FPGA The chip contains LUT And the number of triggers is very large , It is often tens of thousands ,PLD Generally, you can only do 512 A logical unit , And if you divide the chip price by the number of logical units ,FPGA The average logical unit cost of is much lower than PLD. So if a lot of triggers are used in the design , For example, designing a complex sequential logic , So use FPGA Is a good choice .

13： Latch （latch） And triggers （flip-flop） difference ？
      Level sensitive storage periods are called latches . It can be divided into high-level latch and low-level latch , Used for signal synchronization between different clocks .
      Bistable memory elements with cross coupled gates are called flip flops . It is divided into rising edge trigger and falling edge trigger . It can be considered as two different level sensitive latches connected in series . The previous latch determines the setup time of the trigger , The latter latch determines the holding time .
The essential difference is ：latch Is the level trigger ,reg It's the edge trigger . Try to use... In timing design reg Trigger .
Behavior description , If it corresponds to all possible input conditions , Some inputs do not correspond to explicit outputs , The system will synthesize latch.
such as ：[email protected]( a or b)  // The lack of else sentence
        begin
           if(a==1)
             q <= b;
         end

14：FPGA What are the two memory resources in the chip ？
 FPGA There are two kinds of memory resources in the chip ： One is called block ram, The other is by LUT Configured as internal memory （ It's distributed ram）.Block ram Consisting of a fixed number of storage blocks , Use BLOCK RAM Resources do not take up additional logical resources , And fast . But it is consumed when used BLOCK RAM A resource is an integer multiple of its block size .

15： What is clock jitter ？
Clock jitter refers to the temporary change of the clock cycle at a given point of the chip , That is to say, the clock cycle may be lengthened or shortened in different cycles . It is an average of 0 Average variable of .

16：FPGA Use of clock in design ？（ Such as frequency division ）
 FPGA The chip has a fixed clock route , These routes can reduce clock jitter and skew . When the clock needs to be phase shifted or frequency converted , Generally, it is not allowed to perform logical operation on the clock , This will not only increase the clock deviation and jitter , It will also Burr the clock . The general treatment method is to use FPGA The clock manager provided by the chip, such as PLL,DLL or DCM, Or convert the logic to the trigger D Input （ These are also alternatives to clock logic operations ）.

17：FPGA How to realize the delay of synchronous sequential circuit in the design ？
    First of all, let's talk about the delay implementation of asynchronous circuits ： Half of the asynchronous circuit is by adding buffer、 Two level NAND gate, etc （ I haven't used it yet, so I'm not sure ）, But this is not suitable for synchronous circuit to realize delay .
In synchronous circuit , For large and special delay , Half of the counter is generated by high-speed clock , The time delay is controlled by a counter ; For smaller delays , You can take a shot through the trigger , But this will only delay One clock cycle .

18：FPGA Can be synthetically implemented as RAM/ROM/CAM Three resources and their considerations ？
Three resources ：block ram; trigger （FF）, Lookup table （LUT）;
matters needing attention ：1： It's generating RAM Wait for the storage unit , Should be the first choice block ram resources ; There are two reasons ： First of all ： Use block ram And so on , Can save more FF and 4-LUT And so on . Use block ram Can be said to be “ No need for nothing ”, Is to maximize device performance , A manifestation of cost saving ; second ：block ram It is a configurable hardware structure , Its reliability and speed are the same as that of LUT and register Built storage has advantages .2： clarify FPGA The hardware structure of , The rational use of block ram resources ;3： analysis block ram Capacity , Use it efficiently block ram resources ;4： Distributed ram resources （distribute ram）

19：Xilinx And global clock resources DLL Related hardware primitives ： Commonly used related to global clock resources Xilinx Device primitives include ：IBUFG,IBUFGDS,BUFG,BUFGP,BUFGCE,BUFGMUX,BUFGDLL,DCM etc. . For the explanation of each device primitive, please refer to 《FPGA Design guidelines 》p50 part .

20：HDL The hierarchical concept of language ？
    HDL Language is hierarchical 、 Type of , The most commonly used hierarchy concepts are system and standard level 、 Functional module level , Behavior level , Register transfer level and gate level .

21： The principle and structure of lookup table ？
Lookup table （look-up-table） Referred to as LUT,LUT It's essentially one RAM. at present FPGA Use more 4 Input LUT, So every one LUT It can be seen as a being 4 Bit address line 16x1 Of RAM. When the user passes the schematic or HDL After language describes a logic circuit ,PLD/FPGA The development software will automatically calculate all possible results of the logic circuit , And write the results in advance RAM, such , Every time Inputting a signal for logic operation is equivalent to inputting an address for table lookup , Find out what the address corresponds to , Then output it

22：ic Design front-end to back-end processes and eda Tools ？
    Design front end is also called logic design , Back end design is also called physical design , There is no strict boundary between the two , Generally, the design related to process is the back-end design .
       1： Specification formulation ： Customers put forward design requirements to chip design companies .
       2： Detailed design ： Chip design company （Fabless） According to the customer's specifications , Come up with design solutions and specific implementation architecture , Partition module function . At present, the verification of the architecture is generally based on systemC Language , The simulation of the model after consideration can use systemC Simulation tool for . for example ：CoCentric and Visual Elite etc. .
       3：HDL code ： Design input tools ：ultra ,visual VHDL etc.
       4： Simulation verification ：modelsim
       5： Logic synthesis ：synplify
       6： Static time series analysis ：synopsys Of Prime Time
       7： Formal verification ：Synopsys Of Formality.

23： The parasitic effect is ic How to overcome and utilize them in design （ This is my understanding , The original question seems to say ,ic Designed
How will the feedback of parasitic effect affect the designer's design scheme ）？

24： use filp-flop and logic-gate To design a 1 Bit adders , Input carryin and current-stage, Output
carryout and next-stage？
process(sig_intel)
begin
       case sig_intel is
              when "000" => carryout <= '0';
                                   next_state <= '0';
              when "001" => carryout <= '1';
                                   next_state <= '0';
              when "010" => carryout <= '1';
                                   next_state <= '0';
              when "011" => carryout <= '0';
                                   next_state <= '1';
              when "100" => carryout <= '1';
                                   next_state <= '0';
              when "101" => carryout <= '0';
                                   next_state <= '1';
              when "110" => carryout <= '0';
                                   next_state <= '1';
              when "111" => carryout <= '1';
                                   next_state <= '1';
              when others => carryout <= 'X';
                                   next_state <= 'X';
       end case;
end process;

25： Design an automatic beverage vending machine , drinks 10 Cents , Coins have 5 Points and 10 There are two kinds , And consider change ,
1. Draw fsm（ Finite state machine ）
2. use verilog Programming , The grammar should conform to fpga Design requirements
3. Tools and general design process that can be used in design engineering ？
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity drink_auto_sale is
         port(clk: in std_logic;
                   reset:in std_logic;
                   sw101:in std_logic;
                   sw102:in std_logic;
                   buy : out std_logic;
                   back: out std_logic);
end drink_auto_sale;
architecture Behavioral of drink_auto_sale is
type state_type is(st0,st1);
signal cs ,ns : state_type;
begin
process(clk,reset)
begin
         if(reset = '1') then
                   cs <= st0;
         elsif(clk'event and clk = '1') then   
                   cs <= ns;
         end if;
end process;

process(reset ,cs)
begin
         case cs is
                   when st0 =>        if( sw101 = '1') then
                                                                 ns <= st1;
                                                                 buy<= '0';
                                                                 back<= '0';
                                                        elsif(sw102 = '1') then
                                                                 ns <= st0;
                                                                 buy<= '1';
                                                                 back <= '0';
                                                        else
                                                                 ns <= st0 ;
                                                                 buy <= '0';
                                                                 back <= '0';
                                                        end if;
                   when st1 => if(sw101 = '1') then
                                                                 ns <= st0;
                                                                 buy <= '1';
                                                                 back <= '0';
                                                        elsif(sw102 = '1') then
                                                                 ns <= st0;
                                                                 buy <= '1';
                                                                 back <= '1';
                                                        end if;
                   when others => ns <= st0;
                                                                 buy<= '0';
                                                                 back <= '0';
         end  case;
end process;
end Behavioral;
set up Counting process ： Set three states ：0 branch ,5 branch ; When the state of 0 time-sharing , Received 5 After the split signal pulse, it turns to 5 branch ; Received 10 Split signal pulse , go to 0 Sub state , Pop up the drink at the same time , No change ; state by 5 time-sharing , Accept to 5 Sub signal , Pop up the drink , No change , return 0 Sub state ; When you receive 10 Sub state , Pop up the drink , Give change , And return to zero .
Design tools used ：ISE7.1,modelsim,synplify
（ I don't know why the above state machine is designed in synplify Of RTL view You can't see the state machine flow chart in , So the state transition diagram is not drawn ）.

26： What is? " Line and " Logic , To achieve it , What are the specific requirements for hardware characteristics ?
Line and logic are functions that can be realized by connecting two output signals . On hardware , Use oc Door to achieve , Because you don't have to oc The door may cause the charging current to be too high , And burn out the logic gate . At the same time, a pull-up resistor shall be added to the output port .Oc The gate is the open collector gate .

27： What is the phenomenon of competition and adventure ? How to judge ? How to eliminate ?
    In Combinational Circuits , After a certain input variable is transmitted through different channels , The time to reach a junction in the circuit is first and then , This phenomenon is called competition ; The phenomenon that the circuit output is instantaneously wrong due to competition is called adventure .（ That is, the glitch caused by competition is called adventure ）. Judgment method ： Algebra （ If there are opposite signals in Boolean expressions, competition and adventure may occur ）; Karnaugh map ： There are two tangent Carnot circles and they are The cut is not surrounded by other Cano circles , There may be competitive risks ; Experimental method ： Oscilloscope observation ;
resolvent ：1： Add filter circuit , Eliminate the effect of burrs ;2： Add strobe signal , Avoid burrs ;3： Add redundant items to eliminate logical risks .

28： You know those common logic levels ?TTL And COMS Can the levels be directly interconnected ？
Common logic level ：TTL、CMOS、LVTTL、LVCMOS、ECL（Emitter Coupled Logic）、PECL（Pseudo/Positive Emitter Coupled Logic）、LVDS（Low Voltage Differential Signaling）、GTL（Gunning Transceiver Logic）、BTL（Backplane Transceiver Logic）、ETL（enhanced transceiver logic）、GTLP（Gunning Transceiver Logic Plus）;RS232、RS422、RS485（12V,5V,3.3V）;

There is also an answer ： Common logic level ：12V,5V,3.3V.TTL and CMOS No direct interconnection , because TTL Is in 0.3-3.6V Between , and CMOS There is 12V Yes, there are 5V Of .CMOS The output is connected to TTL Can be directly interconnected .TTL Receive CMOS You need to add a pull-up resistor to the output port 5V perhaps 12V.

cmos The high and low levels of are respectively :Vih>=0.7VDD,Vil<=0.3VDD;Voh>=0.9VDD,Vol<=0.1VDD.
ttl For the :Vih>=2.0v,Vil<=0.8v;Voh>=2.4v,Vol<=0.4v.

use cmos Can drive directly ttl; Add the pull resistance ,ttl Can drive cmos.

1、 When TTL Circuit drive COMS When the circuit is , If TTL The high level of the circuit output is lower than COMS The lowest high level of a circuit （ It's usually 3.5V）, And that's where we need to be TTL The output terminal of is connected with pull-up resistance , To increase the value of the output high level .
2、OC The gate circuit must have a pull resistance , To increase the output level value .
3、 In order to increase the driving ability of the output pin , Some SCM pins often use pull-up resistance .
4、 stay COMS On chip , In order to prevent damage caused by static electricity , The pins that are not used should not be suspended , Generally, the pull-up resistance is connected to reduce the input impedance , Provide discharge access .
5、 The pin of the chip plus the pull resistance to improve the output level , So as to improve the noise tolerance of the chip input signal and enhance the anti-interference ability .
6、 Improve the anti electromagnetic interference ability of the bus . Pin hanging in the air is easy to accept electromagnetic interference from the outside .
7、 In long line transmission, the resistance mismatch is easy to cause reflected wave interference , Plus the pull-down resistance is the resistance match , Effectively suppress the interference of reflected wave .

The selection principles of pull-up resistance include :
1、 It should be large enough considering the power saving and the chip's current filling ability ; High resistance , The current is small .
2、 It should be small enough to ensure enough driving current ; Low resistance , High current .
3、 For high-speed circuits , Too much pull-up resistance may flatten the edge . Take the above three points into consideration , Usually in 1k To 10k Selection between . There's a similar thing about pull-down resistance .

OC The gate circuit must have a pull resistance , To increase the output level value .
OC The gate circuit shall output “1” When you need to add a pull resistance, there is no high level at all
Sometimes we use OC The door is driven （ For example, control a LED） When the current is filled, the pulling resistance can not be added
OC The door can realize “ Line and ” operation
OC The gate is the collector Open the way Output
In short, the addition of pull resistance can improve the driving ability .

29：IC The difference between synchronous reset and asynchronous reset in the design ？
Synchronous reset acquires a reset signal at the edge of the clock , Complete the reset action . Asynchronous reset regardless of clock , As long as the reset signal meets the conditions , Complete the reset action . Asynchronous reset requires high reset signal , No burrs , If its relationship to the clock is uncertain , Metastable states may also occur .

30：MOORE And MEELEY The characteristics of the state machine ？
       Moore The output of the state machine is only related to the current state value , And only when the edge of the clock comes will there be a state change .
       Mealy The output of the state machine is not only related to the current state value , And related to the current input value .

31： In multi time domain design , How to process signals across time domain ？
    Synchronous processing is required for signal communication between different clock domains , This can prevent the metastable signal of the first stage flip-flop in the new clock domain from affecting the lower logic .

Signals are synchronized across clock domains ： When a single signal crosses the clock Domain time , Two level triggers can be used to synchronize ; The data or address bus can be asynchronous when it crosses the clock domain fifo To achieve clock synchronization ; The third method is to use handshake signals .

32： Talk about static 、 Advantages and disadvantages of dynamic timing simulation ？

Static timing analysis uses the exhaustive analysis method to extract all timing paths of the whole circuit , Calculate the propagation delay of the signal on these paths , Check the signal Whether the establishment and holding time meet the timing requirements , Through the analysis of maximum path delay and minimum path delay , Identify errors that violate timing constraints . It can exhaust all paths without input vectors , And the running speed is very fast 、 Less memory , It can not only check the timing function of the chip design comprehensively , Moreover, the results of time series analysis can be used to optimize the design , Therefore, static timing analysis has been increasingly used in digital integrated circuits Verification of road design .

Dynamic timing simulation is the usual simulation , Because it is impossible to produce a complete test vector , Overwrite every path in the gate level netlist . Therefore, in dynamic timing analysis , Unable to expose possible timing problems on some paths ;

33： A four grade Mux, The second stage signal is the key signal How to improve timing.？
    The key ： Put the second stage signal to the last output stage for output , At the same time, pay attention to modifying the chip selection signal , Ensure that its priority is not modified .（ Why? ？）

34： Give a diagram of the gate level , The transmission delay of each gate is also given , Ask what the critical path is , Also ask for input , Make the output dependent on the critical path ？

35： Why in a standard inverter P The width length ratio of the tube is larger than N The aspect ratio of the tube is large ?
        Related to carriers ,P A tube is a hole conducting ,N Tubes are electrically conductive , The mobility of electrons is greater than that of holes , Under the same electric field ,N The current of the tube is greater than P tube , So increase P The aspect ratio of the tube , Make it symmetrical , In this way, the rising time and falling time of both can be equal 、 The noise tolerance of high and low levels is the same 、 Equal charging and discharging time .

42：A,B,C,D,E Vote , The majority is subordinate to the minority , The output is F( That is, if A,B,C,D,E in 1 The number ratio of 0 many , that F Output is 1, otherwise F by 0), Use NAND gate to realize , There is no limit to the number of entries ？
  F= ABC + ABD + ABE +ACD + ACE+ ADE + BCD + BCE + CDE + BDE

45：latch And register The difference between , Why use more now register. Behavior level description latch How to produce ？
       latch Is the level trigger ,register It's the edge trigger ,register Action triggered by the same clock edge , It conforms to the design idea of synchronous circuit , and latch It belongs to asynchronous circuit design , It often leads to difficulties in timing analysis , Inappropriate application latch It will waste a lot of chip resources .

46： use D The flip-flop is a circuit that divides the frequency into two parts ？ Draw the logic circuit ？
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity two_de_fre is
         port(clk: in std_logic;
                            reset:in std_logic;
                            clk_out: out std_logic) ;
end two_de_fre;
architecture Behavioral of two_de_fre is
signal sig_clk: std_logic;
begin
process(clk)
begin
         if(reset = '1') then
                   sig_clk <= '0';
         elsif(clk'event and clk = '1') then
                   sig_clk <= not sig_clk;
         end if;
end process;
clk_out <= sig_clk;      
end Behavioral;
This method is generally not used in display engineering design , Two frequency division is generally through DCM To achieve . adopt DCM The obtained frequency division signal has no phase difference .

47： What is a state diagram ？
        The state diagram describes the state transition law of sequential logic circuit and the relationship between output and input in the form of geometry .

48： Use the design method you are familiar with to design a preset initial value 7 Binary cycle counter ,15 The base number ？
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seven_counter is
         port(reset:in std_logic;
                            clk: in std_logic;
                            counter_out std_logic_vector(2 downto 0));
end seven_counter;
architecture Behavioral of seven_counter is
signal sig_counter : std_logic_vector(2 downto 0);
begin
process(reset,clk)
begin
         if(reset = '1') then
                   sig_count <= "101" ;  -- The initial value is 5
         elsif(clk'event and clk = '1') then
                   sig_count <= sig_count + 1;
         end if;
end process;
counter_out <= sig_counter;                                                                                                               
end Behavioral;

15 The design of binary counter only needs to counter_out and sig_counter Change it to 4 Just a little bit ;

49： What kinds of programmable logic devices do you know ？
       PAL,PLD,CPLD,FPGA

50： use VERILOG or VHDL Write a piece of code , Realize the elimination of a glitch？
The burr can be eliminated by passing the transmitted signal through a two-stage trigger .（ This is my own way ： It is necessary to meet certain conditions to remove burrs in this way , There is no guarantee that ）

51：sram,falsh memory, And dram The difference between ?
sram： Static random access memory , Fast access , But the capacity is small , Data will be lost after power failure , Unlike DRAM Need to keep REFRESH, High manufacturing cost , Usually used as a cache (CACHE) Memory usage
flash： Flash memory , Slow access , Large capacity , Data will not be lost after power failure
dram： Dynamic RAM , It must be strengthened again and again (REFRESHED) Potential difference , Otherwise, the potential difference will be reduced so that there is not enough energy to show what state each memory unit is in . Price ratio sram cheap , But access is slow , High power consumption , It is often used as the memory of a computer .

52： There are four ways to reuse , Frequency division multiplexing , Write the other three ？
        Four reuse methods ： Frequency division multiplexing （FDMA）, Time division multiplexing （TDMA）, Code division multiplexing （CDMA）, Wavelength division multiplexing （WDM）

53：ASIC When to revise in the design process Setup time violation and Hold time violation? How to fix ？
See setup time and hold time above

54： A combinational logic circuit is given , It is required to analyze the logic function .
        The analysis of so-called combinational logic circuits , Is to find out the relationship between the output and input of a given logic circuit , And point out the logic function of the circuit .
        The analysis process is generally carried out according to the following steps ：
1： According to the given logic circuit , Start at the input , The logic function expression at the output end is derived step by step .
2： List the truth table according to the output function expression ;
3： Summarize the logic function of the circuit in words ;

55： How to prevent metastable ？
1 Reduce the system clock frequency
2 With faster response FF
3 Introduce synchronization mechanism , Prevent metastable propagation （ You can use the two-stage trigger mentioned above ）.
4 Improve clock quality , Use a clock signal with fast edge changes

56： The content of Kirchhoff's Theorem
Kirchhoff's law includes current law and voltage law ：
Current law ： In a lumped circuit , Any time , For any node , The algebraic sum of branch currents of all outgoing nodes is equal to zero .
The law of voltage ： In a lumped circuit , Any time , Along any circuit , The algebraic sum of all branch voltages is equal to zero .

57： Describe the concept of feedback circuits , List their applications .
feedback , In the circuit system , Input the electric quantity in the output circuit into the input circuit .
The types of feedback are ： Voltage series negative feedback 、 Current series negative feedback 、 Voltage parallel negative feedback 、 Current parallel negative feedback .
The advantages of negative feedback ： Reduce the gain sensitivity of the amplifier , Change the input resistance and output resistance , Improve the linear and nonlinear distortion of the amplifier , Effectively expand the passband of the amplifier , Automatic adjustment function .
Characteristics of negative voltage feedback ： The output voltage of the circuit tends to remain constant .
Characteristics of negative current feedback ： The output current of the circuit tends to remain constant .

58： The difference between active filter and passive filter
Passive filter ： This kind of circuit mainly has passive components R、L and C form
Active power filter ： Integrated OP AMP and R、C form , With no inductance 、 Small volume 、 Advantages such as light weight .
The open-loop voltage gain and input impedance of the integrated operational amplifier are very high , Low output resistance , The active filter circuit also has the function of voltage amplification and buffer . But the bandwidth of integrated operational amplifier is limited , Therefore, it is difficult for the current active filter circuit to work at a high frequency .

59： What is called OTP slice 、 Mask , What is the difference between the two ？
OTP means one time program, One time programming
MTP means multi time program, Multiple programming
OTP（One Time Program） yes MCU A type of memory for
MCU According to its memory type, it can be divided into MASK( Mask )ROM、OTP( One time programmable )ROM、FLASHROM Other types .
MASKROM Of MCU Cheapness , But the program has been solidified at the factory , Suitable for applications where the program is fixed ;
FALSHROM Of MCU Programs can be rewritten over and over , Very flexible , But the price is higher , Suitable for price insensitive applications or development purposes ;
OTP ROM Of MCU The price is somewhere between the first two , At the same time, it has one-time programmable ability , Fit requires some flexibility , It also requires low-cost applications , In particular, the functions are constantly renovated 、 Electronic products requiring rapid mass production .
60、 The single chip microcomputer does not run after it is powered on , First check what ？
First, confirm whether the power supply voltage is normal . Use a voltmeter to measure the voltage between the ground pin and the power pin , See if it's the power supply voltage , For example, commonly used 5V.
The next step is to check whether the voltage of the reset pin is normal . Measure the voltage value of pressing the reset button and releasing the reset button respectively , See if it's right .
Then check whether the crystal oscillator vibrates , Generally use an oscilloscope to see the waveform of the crystal oscillator pin , Note that the oscilloscope probe should be used “X10” files . Another way is Measure... Under reset state IO Port level , Press and hold the reset key , Then measure IO mouth （ No external pull-up connection P0 Except the mouth ） The voltage of , See if it is high level , If not high , Most of the reason is that the crystal oscillator did not There is vibration .
Another thing to note is , If on-chip ROM Words （ In most cases , There are few external extensions available now ROM Of course. ）, Be sure to will EA The pins are pulled up , Otherwise, the program will run randomly . Sometimes an emulator can , But it's not good to burn the film , It's often because EA The pin is not pulled high （ Of course , There is only one reason why the crystal oscillator did not start ）. On the course Check at what time , Generally, the fault can be eliminated . If the system is unstable , Sometimes it is caused by poor power filtering . Connect a between the power pin and the ground pin of the single chip microcomputer 0.1uF The capacitance of will be improve . If the power supply has no filter capacitor , Then a larger filter capacitor needs to be connected , for example 220uF Of . When the system is unstable , You can try it with a capacitor （ The closer you get to the chip, the better ）.

61： Give it to reg Of setup,hold Time , Find the of intermediate combinatorial logic delay Range
       Delay < period - setup – hold

62： The clock period is T, trigger D1 The maximum register to output time of is T1max, The minimum is T1min. The maximum delay of combinational logic circuit is T2max, The minimum is T2min. ask , trigger D2 The time of its establishment T3 And holding time
T3setup>T+T2max,T3hold>T1min+T2min

66： The difference between blocking assignment and non blocking assignment ？
Nonblocking assignment ： The assignment statements in the block are assigned at the same time , It is generally used in the description of sequential circuits .
Block assignment ： The operation of the next sentence can only be performed after the assignment statement is completed , It is generally used in the description of combinatorial logic .

67：74、 use FSM Realization 101101 Sequence detection module .
a Is the input ,b Is the output , If a Continuous input is 1101 be b Output is 1, Otherwise 0.
for example a： 0001100110110100100110
b： 0000000000100100000000
Please draw state machine; Please use RTL Describe it state machine.（ Unknown ）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity detect_stream is
         port(clk: in std_logic;
                            reset: in std_logic;
                            data: in std_logic;
                            result : out std_logic);
end detect_stream;
architecture Behavioral of detect_stream is
type state_type is (idle,st0,st1,st2);
signal cs ,ns : state_type;
signal sig_result :std_logic;
begin
process(clk,reset)
begin
         if(reset = '1') then
                   cs <= idle;
                   result <= '0';
         elsif(clk'event and clk = '1')  then
                   cs  <= ns;
                   result <= sig_result;
         end if;
end process;
process(cs,clk)
begin
                   case cs is
                            when idle => if(data = '1') then
                                                                                    ns <= st0;
                                                                                    sig_result <= '0';
                                                                           else
                                                                                    ns <= idle;
                                                                                    sig_result <= '0';
                                                                           end if;
                            when st0 => if(data = '1') then
                                                                           ns <= st1;
                                                                           sig_result <= '0';
                                                                 else
                                                                           ns <= idle;
                                                                           sig_result <= '0';
                                                                 end if;
                            when st1 => if(data = '0')then
                                                                           ns <= st2;
                                                                           sig_result <= '0';
                                                                 else
                                                                           ns <= idle;
                                                                           sig_result <= '0';
                                                                 end if;
                            when st2 => ns <= idle;
                                                                 if(data = '1') then
                                                                           sig_result <= '1';
                                                                 else
                                                                           sig_result <= '0';
                                                                 end if;
                            end case;
end process;
end Behavioral;
State diagram ：

68： use verilog/vhdl Write a fifo controller ( Including empty , full , Half full signal ).
reg[N-1:0] memory[0:M－1]; Definition FIFO by N Bit word length capacity M
Eight always Module implementation , Two for reading and writing FIFO, Two for generating header addresses head And ending address tail, One produces counter Count , The remaining three bases counter The value of generates null , full , A half full signal produces a null , full , Half full signal .

69： An existing user needs an integrated circuit product , The product is required to realize the following functions ：y=lnx, among ,x by 4 Bit binary integer input signal .y Output for binary decimal , Two decimal places are required . The supply voltage is 3~5v Suppose the company receives the project , We are responsible for the design of the product , Try to discuss the whole design process of the product .（ Shilan microelectronics ）

70：iir,fir Similarities and differences of filters
IIR The unit response is an infinite pulse sequence FIR The unit response is finite  
iir The accuracy of amplitude frequency characteristic is very high , Not linear phase , It can be applied to audio signals insensitive to phase information ;
fir The accuracy of amplitude frequency characteristic is better than iir low , But linear phase , That is, signals with different frequency components pass through fir Their time difference remains unchanged after the filter . This is a very good property .
    In addition, the limited unit response is also conducive to the processing of digital signals , Easy to program , The time delay for calculation is also small , This is important for real-time signal processing

71: use Verilog To design a 5 Frequency divider .
       5 frequency division , Odd frequency division can be done in a similar way , Just change div1 and div2 Parameters of .div1 Divide odd numbers by frequency 2 The remainder of . Different waveforms are triggered by rising delay and falling delay respectively , Finally, odd frequency division is generated by superposition .
module divfreq(clk, clk1x, rst, clk1xpose, clk1xnege, coutpose, coutnege);
input clk;
input rst;
output clk1x;
output clk1xpose;
output clk1xnege;
output[2:0] coutpose;
output[2:0] coutnege;
reg clk1xpose;
reg clk1xnege;
reg[2:0] coutpose;
reg[2:0] coutnege;
parameter div1 = 2 , div2 = 4;  // div1 ＝ 5 / 2, div2 = 5 - 1
assign clk1x = clk1xpose | clk1xnege;
[email protected](posedge clk or negedge rst)
 begin
  if(!rst)
 
    clk1xpose = 0;
 
  else if(coutpose == div1)
    clk1xpose = ~clk1xpose;
  else if(coutpose == div2)
    clk1xpose = ~clk1xpose;
  else
    clk1xpose = clk1xpose;
 end
[email protected](negedge clk or negedge rst)
 begin
  if(!rst)
 
    clk1xnege = 0;
 
  else if(coutnege == div1)
   clk1xnege = ~clk1xnege;
  else if(coutnege == div2)
   clk1xnege = ~clk1xnege;
  else
   clk1xnege = clk1xnege;
 end
[email protected](posedge clk or negedge rst)
 begin
  if(!rst)
   coutpose = 0;
  else if(coutpose == div2)
   coutpose = 0;
  else
   coutpose = coutpose + 1;
 end
[email protected](negedge clk or negedge rst)
 begin
  if(!rst)
   coutnege = 0;
  else if(coutnege == div2)
   coutnege = 0;
  else
   coutnege = coutnege + 1;
 end
endmodule

75: 63、 use D Trigger implementation 2 Times the frequency Verilog describe ? 
module divide2( clk , clk_o, reset); 
   input     clk , reset; 
   output   clk_o; 
   wire in;   
reg out ; 
   always @ ( posedge clk or posedge reset) 
     if ( reset) 
       out <= 0; 
         else 
           out <= in; 
       assign in = ~out; 
       assign clk_o = out; 
     endmodule
76: Write asynchrony D Trigger verilog module.( Yangzhi electronic written test ) 
module dff8(clk , reset, d, q); 
input         clk; 
input         reset; 
input   [7:0] d; 
output [7:0] q; 
reg   [7:0] q; 
always @ (posedge clk or posedge reset) 
   if(reset) 
     q <= 0; 
   else 
     q <= d; 
endmodule

77：
The trial VHDL or VERILOG、ABLE describe 8 position D Trigger logic . 
module dff8(clk , reset, d, q);
input        clk;
input        reset;
input  [7:0] d;
output [7:0] q;
reg   [7:0] q;
always @ (posedge clk or posedge reset)
   if(reset)
     q <= 0;
   else
     q <= d;
endmodule

78： Noun IRQ,BIOS,USB,VHDL,SDR
IRQ:   Interrupt ReQuest
BIOS:  Basic Input Output System
USB:  Universal Serial Bus
VHDL: VHIC Hardware Deion Language
SDR:  Single Data Rate

79：23  What is PC Chipset? 
Chipset （Chipset） It's the core part of the motherboard , According to the arrangement position on the motherboard , It is usually divided into North Bridge chip and South Bridge chip . Beiqiao chip provides a pair of CPU Type and dominant frequency of 、 Type and maximum capacity of memory 、ISA/PCI/AGP slot 、ECC Error correction and other support . Nanqiao chip provides a pair of KBC（ Keyboard controller ）、RTC（ Real time clock controller ）、USB（ Universal serial bus ）、Ultra DMA/33(66)EIDE Data transmission mode and ACPI（ Advanced energy management ） And so on . Among them, Beiqiao chip plays a leading role , Also known as the main bridge （Host Bridge）.
In addition to the most common north-south bridge structure , At present, chipsets are developing towards a more advanced accelerated hub architecture ,Intel Of 8xx Series chipset is the representative of this kind of chipset , It integrates some subsystems such as IDE Interface 、 Sound effect 、MODEM and USB Directly connected to the main chip , Be able to provide PCI Double the bus width , Reached 266MB/s.