Cadence physical library lef file syntax learning [continuous update]

I am a Snow fish , a FPGA lovers , The research direction is FPGA Architecture exploration .

Official account , Pull you in “IC Design communication group ”.

One 、LEF brief introduction

LEF yes Library Exchange Format Abbreviation , Describes the library information of the design , The library data includes layer、via、placement site type 、macro cell Definition .

1.1 General rules

1. Identifier such as net name 、cell name Are limited to 2048 Within characters
2. Distance is defined in microns .
3. The distance accuracy is determined by UNITS Statement control
4. LEF The statement is semicolon (;) ending ． There must be a space between the last character of the statement and the semicolon .

1.2 management LEF file

Can be in a LEF The file defines all the library information required for the design ; But doing so will create a large file that is complex and difficult to manage . So you can split the library information into two files , One is “technology”LEF file , The other is “cell library”LEF file .

• technology LEF file： process LEF The document contains all process information of the design , For example, layout and routing design rules and layer processing information . One technology LEF The file can include any of the following LEF sentence ：

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[UNITS statement]
[MANUFACTURINGGRID statement]
[USEMINSPACING statement]
[CLEARANCEMEASURE statement ;]
[PROPERTYDEFINITIONS statement]
[FIXEDMASK ;]
[LAYER (Nonrouting) statement
 | LAYER (Routing) statement] ...
[MAXVIASTACK statement]
[VIA statement] ...
[VIARULE statement] ...
[VIARULE GENERATE statement] ...
[NONDEFAULTRULE statement] ...
[SITE statement] ...
[BEGINEXT statement] ...
[END LIBRARY]

• cell library LEF file : Cell library LEF The file contains the macro and standard unit information required for the design .
  library LEF The file can contain any of the following LEF sentence ：

[VERSION statement]
[BUSBITCHARS statement]
[DIVIDERCHAR statement]
[VIA statement] ...
[SITE statement]
[MACRO statement
  [PIN statement] ...
  [OBS statement ...] ] ...
[BEGINEXT statement] ...
[END LIBRARY]

notes ： Read LEF When you file , Must read first technology LEF file, Because in cell library LEF file Will be used in
technology LEF file Some library information defined .

Two 、Layer (Cut)

Define each by assigning names and design rules cut layer . Every cut Layers must be defined separately . Define layers from the bottom up order . for example ：

poly masterslice
cut01 cut
metal1 routing
cut12 cut
metal2 routing
cut23 cut
metal3 routing

This should be easy to understand for friends who have made territory , Namely poly + via + metal1 + via1 + metal2 + via2 +… Multi stack ,cut Layers are actually used to define vias Of .

grammar ：

LAYER layerName
TYPE CUT ;
[MASK maskNum ;]
[SPACING cutSpacing
   [CENTERTOCENTER]
   [SAMENET]
   [ LAYER secondLayerName [STACK]
    | ADJACENTCUTS {
    2 | 3 | 4} WITHIN cutWithin [EXCEPTSAMEPGNET]
    | PARALLELOVERLAP
    | AREA cutArea
   ]
;] ...
[SPACINGTABLE ORTHOGONAL
       {
    WITHIN cutWithin SPACING orthoSpacing} ... ;]
[ARRAYSPACING [LONGARRAY] [WIDTH viaWidth] CUTSPACING cutSpacing
   {
    ARRAYCUTS arrayCuts SPACING arraySpacing} ... ;]
[WIDTH minWidth ;]
[ENCLOSURE [ABOVE | BELOW] overhang1 overhang2
  [ WIDTH minWidth [EXCEPTEXTRACUT cutWithin]
  | LENGTH minLength]
;] ...
[PREFERENCLOSURE [ABOVE | BELOW] overhang1 overhang2 [WIDTH minWidth] ;] ...
[RESISTANCE resistancePerCut ;]
[PROPERTY propName propVal ;] ...
[ACCURRENTDENSITY {
    PEAK | AVERAGE | RMS}
  {
     value
  | FREQUENCY freq_1 freq_2 ... ;
      [CUTAREA cutArea_1 cutArea_2 ... ;]
      TABLEENTRIES
       v_freq_1_cutArea_1 v_freq_1_cutArea_2 ...
       v_freq_2_cutArea_1 v_freq_2_cutArea_2 ...
       ...
  } ;]
[DCCURRENTDENSITY AVERAGE
  {
     value
  | CUTAREA cutArea_1 cutArea_2 ... ;
      TABLEENTRIES value_1 value_2 ...
  } ;]
[ANTENNAMODEL {
    OXIDE1 | OXIDE2 | OXIDE3 | OXIDE4} ;] ...
[ANTENNAAREARATIO value ;] ...
[ANTENNADIFFAREARATIO {
    value | PWL ( ( d1 r1 ) ( d2 r2 ) ...)} ;] ...
[ANTENNACUMAREARATIO value ;] ...
[ANTENNACUMDIFFAREARATIO {
    value | PWL ( ( d1 r1 ) ( d2 r2 ) ...)} ;] ...
[ANTENNAAREAFACTOR value [DIFFUSEONLY] ;] ...
[ANTENNACUMROUTINGPLUSCUT ;]
[ANTENNAGATEPLUSDIFF plusDiffFactor ;]
[ANTENNAAREAMINUSDIFF minusDiffFactor ;]
[ANTENNAAREADIFFREDUCEPWL
   ( ( diffArea1 diffAreaFactor1 ) ( diffArea2 diffAreaFactor2 ) ...) ; ]
END layerName

example ：

LAYER mcon
  TYPE CUT ;

  WIDTH 0.17 ;                # Mcon 1
  SPACING 0.19 ;              # Mcon 2
  ENCLOSURE BELOW 0 0 ;       # Mcon 4
  ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5

  ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ;
  DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC

END mcon

There are many grammars involved here , I will not explain them one by one , When we use it later , Update again , First, explain the above examples .

sentence	describe
WIDTH	Through hole width （ Square ）
SPACING	Minimum spacing between through holes
ENCLOSURE	BELOW : Specifies the minimum distance between the through hole boundary and the adjacent metal layer boundary below ABOVE： Specifies the minimum distance between the through hole boundary and the upper adjacent metal layer boundary

Look at the picture to explain , The width of the through hole refers to the middle square in the figure above （ It's a bit like a rectangle ） Width ,overhang1 It refers to the distance between the left and right sides of the through hole and the metal boundary ,overhang2 It refers to the distance between the upper and lower sides of the through hole and the metal boundary .

and SPACING Is the spacing between the through holes .

3、 ... and 、Layer(Masterslice or Overlap)

Define... In the design MasterSlice（ Non wiring ） or overlap layers. Masterslice layers Usually polysilicon layer , Only when the macro cell is on the polysilicon layer pins Will be defined .

grammar ：

LAYER layerName
TYPE {
    MASTERSLICE | OVERLAP} ;
[MASK maskNum ;]
[PROPERTY propName propVal ;] ...
[PROPERTY LEF58_TYPE
   "TYPE [NWELL | PWELL | ABOVEDIEEDGE | BELOWDIEEDGE | DIFFUSION | TRIMPOLY | TRIMMETAL | REGION] ];" ;
[PROPERTY LEF58_TRIMMEDMETAL
   "TRIMMEDMETAL metalLayer [MASK maskNum] ]; " ;
END layerName

sentence	describe
LAYER layerName	Specify the name of the layer . This name will be used later when referencing this layer .
TYPE	Specify the purpose of the layer , There are two kinds of - MASTERSLICE : Layer fixed in base array . If pins Appear in the MASTERSLICE Layer , Must define vias To allow the router to connect those pin And the first wiring layer .Masterslice Layers are not allowed to be used for wiring . stay MASTERSLICE A must be defined between the layer and the adjacent wiring layer cut layer - OVERLAP: Layer for line block overlap check .

example ：

LAYER nwell
  TYPE MASTERSLICE ;
  PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
END nwell

LAYER pwell
  TYPE MASTERSLICE ;
  PROPERTY LEF58_TYPE "TYPE PWELL ;" ;
END pwell