当前位置:网站首页>[volatile principle] volatile principle
[volatile principle] volatile principle
2022-07-27 02:10:00 【A duck that cannot enter the water】
volatile principle
One 、 What is? volatile
volatile yes Java A kind of Lightweight synchronization mechanism .Java Language contains two internal synchronization mechanisms : Synchronized block ( Or method ) and volatile Variable , comparison synchronized To solve the problem of shared memory ,volatile It's a lighter choice , He There is no additional overhead cost of context switching . Use volatile Declared variables , Yes When the hedge is updated, it is immediately visible to other threads , In a nutshell , It can lead to other CPU The corresponding cache value in is invalid .volatile Use memory barrier to ensure that instruction reordering does not occur , Solved the problem of memory visibility . however volatile Variable Poor synchronization ( Sometimes it's simpler and less expensive ), And its use is also more error prone .
Two 、volatile principle
Threads read shared variables from main memory to working memory for operation , Write the result to main memory after completion , But that brings visibility issues . for instance , Now let's say we're a two-level cache with dual cores CPU framework , contain L1、L2 Two level cache .
(1) Threads 1 First get the variable X Value , Because the first two levels of cache are empty , So read directly from main memory X, hypothesis X The initial value is 0, Threads 1 After reading, put X Values are changed to 1, Write back to main memory at the same time . At this time, the cache and main memory are shown in the following figure .
(2) Threads 2 Also read variables X Value , because L2 The cache already has a cache X=1, So directly from L2 Cache reads , After that thread 2 hold X It is amended as follows 2, At the same time, write back L2 And main memory . By this time X The value is shown in the figure below .
At this point, the thread 1 If you want to get a variable again X Value , because L1 The cache already has x=1 了 , So at this point Variable memory invisibility problem It came into being. , Threads 2 take X It is amended as follows 2 For threads 1 Come on No perception , The thread 1 I don't know at this time X The value of has become 2 了 .
however , If X Variable usage volatile Embellished words , When a thread 1 Read variables again X Words ,CPU The thread will be forced according to the cache consistency protocol 1 Reload the latest value from main memory to your working memory , Instead of just using the values in the cache .
stay JVM Bottom volatile Is to use Memory barrier To achieve . The memory barrier will provide 3 Features :
(1) It ensures that instructions are reordered without putting the instructions behind them in front of the memory barrier , It doesn't put the previous instructions behind the memory barrier ; That is, when the instruction of memory barrier is executed , All the operations before it have been completed ; In a nutshell , Execute to volatile variable , In front of the All statements have been executed , None of the following statements are executed . And the result of the previous statement is right volatile Variables and statements after them can be seen .
(2) It will Force changes to the cache to be written to main memory immediately ;
(3) If it's a write operation , it It can lead to other CPU The corresponding cache row in is invalid . Make sure When the value is updated, it is immediately visible to other threads .
This article is a study note , It is the understanding of others' knowledge , Together with some personal understandings of myself . If there is an infringement connection, delete . Writing is not easy to , I hope you guys can support me for three times . Be deeply grateful
notes : The source of the original text is https://mp.weixin.qq.com/s/-xFSHf7Gz3FUcafTJUIGWQ
边栏推荐
- STM32 HAL库串口(UART/USART)调试经验(一)——串口通信基础知识+HAL库代码理解
- (atcoder contest 144) f - fork in the road (probability DP)
- [FPGA tutorial case 30] DDS direct digital frequency synthesizer based on FPGA -- frequency accuracy analysis with MATLAB
- JS——初识JS、变量的命名规则,数据类型
- [详解C语言]一文带你玩转函数
- 为啥不建议使用Select *
- 读写分离、主从同步一文搞定
- Mysql数据库-面试题
- [translation] explicit and implicit batch in tensorrt
- JS -- first understand the naming rules and data types of JS and variables
猜你喜欢

mysql的安装

Share 29 chrome plug-ins, and there is always one for you

Machine learning exercise 6 - Support Vector Machines

Text to image论文精读RAT-GAN:文本到图像合成中的递归仿射变换 Recurrent Affine Transformation for Text-to-image Synthesis

科学计算库 —— Matplotlib

Flink1.13.6 detailed deployment method

Solution: various error reports and pit stepping and pit avoidance records encountered in the alchemist cultivation plan pytoch+deeplearning (II)

mysql存储引擎及其区别

解决方案:Win10如何使用bash批处理命令

MySQL stored procedure function
随机推荐
FID index reproduction step on the pit to avoid the pit text generation image FID quantitative experiment whole process reproduction (FR é Chet inception distance) quantitative evaluation experiment s
7.8 锐捷网络笔试
mysql优化概论
PHP processing tree and infinite processing
Docker advanced: detailed explanation of MySQL master-slave replication and redis cluster capacity expansion and reduction configuration cases
7.7 SHEIN希音笔试
[FPGA tutorial case 28] one of DDS direct digital frequency synthesizers based on FPGA -- principle introduction
22FTP
25pxe efficient batch network installation
[FPGA tutorial case 30] DDS direct digital frequency synthesizer based on FPGA -- frequency accuracy analysis with MATLAB
24ssh service
预分频值和自动重装值对中断频率的影响
dlib安装失败解决办法
Shell course summary
Mysql database - interview questions
三种能有效融合文本和图像信息的方法——特征拼接、跨模态注意、条件批量归一化
解决方案:读取两个文件夹里不同名的文件,处理映射不对应的文件
Electron FAQ 61 - must the client run with administrator privileges?
JS 99 multiplication table
平面转换(位移、旋转、缩放)