Popularization of MCU IO port: detailed explanation of push-pull output and open drain output

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source ： Network material

Push pull output : Can output high , Low level , Connect digital devices ;

Open drain output : The output is equivalent to the collector of triode . To get a high level state, you need to pull up the resistor . It is suitable for current drive , Its ability to absorb current is relatively strong ( commonly 20ma within ).

Push pull structure generally means that two triodes are controlled by two complementary signals , Always cut off when one triode is on .

Let's talk about the structure of open collector output first . The structure of open collector output is shown in figure 1 Shown , The transistor collector on the right is not connected to anything , So it's called open collector ( The triode on the left is for inverting , Make the input “0” when , The output is also “0”). For Graphs 1, When the input at the left end is “0” when , The front triode is off ( Collector C With the emitter E Is equivalent to disconnection ), therefore 5V The power goes through 1K The resistance is applied to the triode on the right , The triode on the right turns on ( That is, it is equivalent to a switch closing ); When the input at the left end is “1” when , The front triode turns on , And the back triode is cut off ( It's like the switch is off ).

We're going to figure 1 Simplified mapping 2 The appearance of . chart 2 The switches in the are controlled by software ,“1” Disconnect when ,“0” When closed . It is obvious that , When the switch is closed , The output is directly grounded , So the output level is 0. And when the switch is off , Then the output is suspended , High resistance state . At this time, the level state is unknown , If the next resistive load ( Even a very light load ) To the ground , Then the level of the output is pulled to the low level by the load , So this circuit can't output high level .

Look at Figure 3 . The one in Figure 3 1K The resistance of is the pull-up resistance . If the switch is closed , Then there is an electric current from 1K The resistance and the switch flow through , But because the switch is closed, the other three ports are pulled up inside the belt ), When we want to use the input function , Just set the output port to 1 that will do , This is equivalent to that switch off , And for P0 By mouth , It's the high resistance state .

For open drain (OD) Output , It is very similar to the open collector output . Replace the above triode with a field effect transistor . So the collector becomes a drain ,OC It becomes OD, The principle analysis is the same .

Another output structure is push-pull output . The structure of push-pull output is to replace the pull-up resistor with a switch , When you want to output high level , The upper switch is on , The switch below is off ; And to output a low level , On the contrary . Compared with OC perhaps OD Come on , Such a push-pull structure is high 、 Low level driving capability is very strong . If two output ports with different output levels are connected together , There will be a large current , It is possible to burn out the output port . And it says OC or OD The output will not be like this , Because the current provided by the pull-up resistor is relatively small . If it is push-pull output, it should be set to high resistance state , Both switches must be disconnected at the same time ( Or use a transmission gate on the output port ), This can be used as an input state ,AVR Some of the MCU IO This is the structure of the mouth .

Characteristics and application of open drain circuit

We often encounter open leakage in circuit design (open drain) And open set (open collector) The concept of .

The so-called open drain circuit is mentioned in the concept of “ leak ” Is refers to MOSFET Drain of . Empathy , In an open set circuit “ Set ” It refers to the collector of the triode . An open drain circuit is one in which MOSFET A circuit whose drain is an output . The general usage is to add a pull-up resistor to the circuit outside the drain . A complete open drain circuit should consist of an open drain device and an open drain pull-up resistor . Pictured 1 Shown ：

chart 1

The open drain circuit has the following characteristics ：

1. Using the driving power of external circuits , Reduce IC Internal drive ( Or drive a load higher than the chip power supply voltage ). When IC Inside MOSFET Conduction time , The driving current is from the outside VCC Flow through R pull-up ,MOSFET To GND.IC Only a very low gate drive current is needed inside . Pictured 1.

2. Multiple open drain outputs can be Pin, Connect to a line . formation “ And logic ” Relationship . Pictured 1, When PIN_A、PIN_B、PIN_C After any one goes low , The logic on the open drain line is 0 了 . This is also I2C,SMBus The principle of judging the occupied state of the bus . If it is used as an output, it must be connected with a pull-up resistor . When connected to capacitive load , The falling delay is the transistor in the chip , It is an active drive , Faster ; The rising delay is a passive external resistor , Slow speed . If the speed is required to be high, the resistance shall be small , Power consumption will be high . So the choice of load resistance should consider both power consumption and speed .

3. It can be used to change the voltage of the pull-up power supply , Change transmission level . Pictured 2, IC The logic level of is determined by the power supply Vcc1 decision , The output high level is determined by Vcc2( Supply voltage of pull-up resistor ) decision . In this way, we can use low-level logic to control the output high-level logic ( In this way, you can convert any level ).( For example, adding a pull-up resistor can provide TTL/CMOS Level output, etc .)

chart 2

4. Open a leak Pin Do not connect the external pull-up resistor , Only low level can be output ( So for the classic 51 Single chip microcomputer P0 Speaking of words , If you want to do input and output function, you must add external pull-up resistor , Otherwise, high-level logic cannot be output ). Generally speaking , Open drain is used to connect devices of different levels , For matching levels .

5. The standard open drain pin usually only has the ability to output . Add other judgment circuits , Can have two-way input 、 The ability to output .

6. natural CMOS The output stage is up 、 The next two tubes , Take out the upper pipe OPEN-DRAIN 了 . The main purposes of this output are two ： Level conversion 、 Line and .

7. Lines and functions are mainly used in the case that there are multiple circuits to pull down the same signal , If the circuit does not want to be pulled down , Just output high level , because OPEN-DRAIN The upper pipe was removed , High level is realized by external pull-up resistor .( And normal CMOS Output stage , If one output is high and the other is low , Equal to power short circuit .)

8.OPEN-DRAIN Provides a flexible way to output , But there are also weaknesses , It's the delay that brings the rising edge . Because the rising edge is through external pull-up passive resistance to charge the load , So when the resistance is selected, the delay is small , But the power consumption is high ; On the contrary, the delay is large and the power consumption is small . So if there is a requirement for delay , It is recommended to use the falling edge output .

Attention should be paid to in application ：

1. The principle of open drain is similar to that of open set , In many applications, we use open set circuit instead of open drain circuit . for example , Some input Pin It is required to be driven by open drain circuit . Then our common driving method is to use a triode to form an open set circuit to drive it , Convenient and cost saving . Pictured 3.

2. Pull up resistance R pull-up The resistance value of determines the speed of logic level conversion . The greater the resistance , The lower the speed, the lower the power consumption . vice versa .

Push-Pull Output is generally referred to as push-pull output , stay CMOS There should be more in the circuit CMOS The output is more appropriate , Because in CMOS Inside push-pull The output capacity can't be as big as the two poles . Output capacity IC Internal output pole N tube P Area of pipe . Compared with the open drain output ,push-pull The high and low levels of are determined by IC The power supply is low , You can't simply do logical operations, etc .push-pull It's now CMOS The most used output stage design in the circuit .

Of course open drain It's not without cost , This is the poor driving ability of the output . It is not accurate to say that the driving capacity of the output is very poor , The drive capability depends on IC The power of the last stage transistor in .OD It just brings the delay of rising edge , Because the rising edge charges the load through an external pull-up passive resistor , When the resistance is selected as small, the delay is small 、 But the power consumption is high , On the contrary, the delay is large and the power consumption is small .OPEN DRAIN Provides a flexible way to output , But there is also a price , If time delay is required , It is recommended to use the falling edge to output .

The premise of small resistance and small delay is that the principle of resistance selection should be within the allowable power consumption of the last stage transistor , Experienced designers use logic chips , Will not choose 1 Ohm resistance as pull-up resistance . At the rising edge of the pulse, the power supply charges the load by pulling up the passive resistor , Obviously, the smaller the resistance, the shorter the rise time , At the falling edge of the pulse , Except that the load is discharged through the active transistor , The power supply is also connected to the ground through a pull-up resistor and an on transistor Formation pathway , The problem is the power consumption and power consumption of the chip . Resistance affects the rising edge , Does not affect the falling edge . If you don't care about the rising edge , Pull up the resistance to select as large a point as possible , So as to reduce the electric current . If the rising edge time is required to be high , The selection of resistance should be based on the chip power consumption

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