当前位置:网站首页>[FPGA] Day17 introduction to single bus protocol DS18B20
[FPGA] Day17 introduction to single bus protocol DS18B20
2022-06-10 01:41:00 【Preface to spring breeze】
One 、 Overview of single bus protocol
1、 Introduction to single bus protocol


2、 Introduction to sensors



Two 、DS18B20 summary
1、ds18b20 characteristic

2、ds18b20 structure

3、64 position ROM Encoding mode
Every DS18B20 In slice ROM There is a unique 64 Bit code

4、 Cache
Temporary register
Register bytes 0 And bytes 1 Is read-only , Used to store the temperature value measured by the sensor .
byte 2 High temperature trigger , byte 3 Low temperature trigger , byte 4 Configure registers for .
byte 5、6、7 Reserve space for , byte 8 by CRC check .
Byte 2、3、4 write in EEPROM after , It won't be lost when the power is off .

5、 Temperature sensor
front 5 Bit is sign bit , The binary of negative temperature is in the form of complement , Reverse and add 1 Can be converted to the original code .
-4 The second party is 0.0625,-3 The second party is 0.125,-2 The second party is 0.25,-1 The second party is 0.5.
6、 Configuration register
Where bit 7、 The bit 0-4 It's internal use , Can't cover . Return when read 1
7、DS18B20 Two commands for
ROM command 
Function command
Read the principle of power supply mode : During the read slot , The extra power supply mode will pull the bus high , Parasitic power mode will pull the bus down .
Copy RAM: take TH、TL And configuration register writing EEPROM in , It will not be lost after power failure .
Readjustment EEPROM: After power on , take TH、TL And the configuration register is rewritten into the temporary register .
host must Send a read slot after the read temporary register command or the read power supply mode command ( Reading data ).
host Sure Send a read slot in the temperature conversion command or reset EEPROM After the command ( Read status ).
8、 Sequential logic

On The graph is Write Timeslot
Next The graph is read Timeslot
9、 Initialization sequence diagram
When the host is pulled down, at least 480us Reset signal of , Then release the bus , The slave detects the rising edge pulled up by the pull-up resistance , wait for 15-60us after , Transmit one 60-240us Reset pulse .
The black thick line is pulled down by the host , The grey thick line is made of DS18B20 Pull it down , The black thin wire is pulled up by the pull-up resistor .
边栏推荐
- 生产线往越南转移未必是好选择,三星手机已受累并计划回归韩国
- d内存中映射指令并执行
- 自定义操作日志记录注解
- window. Open (URL) opens the download link for many times and is blocked by the browser. JS realizes circular access to multiple download links
- 加密机与数据库加密产品的区别?
- Kubelet starts a sequence in which pod CRI, CNI and CSI work
- Locust: a powerful tool for microservice performance testing
- What is the difference between encryptors and database encryption products?
- Nodejs报内部错误 TypeError: Cannot read property ‘destroy‘ of undefined的解决方法
- 【Multisim仿真】差分比例放大电路
猜你喜欢
![[games101] Assignment 1 -- MVP (model, view, projection) transformation](/img/55/0b3bf948676abf488b0d5741f71812.png)
[games101] Assignment 1 -- MVP (model, view, projection) transformation

Batch downloading of pictures + mosaic of pictures: multiple pictures constitute the Dragon Boat Festival Ankang

Various utilization forms of map tile data and browsing display of tile data

TRichView and ScaleRichView 设置默认中文

有机金属多孔材料MOF(Fe)包载喜树碱,藤黄酸、吲哚菁绿|RMOF-3包载紫杉醇定制

The transfer of production lines to Vietnam may not be a good choice. Samsung mobile phones have been affected and plan to return to South Korea

Domain Adaptation and Graph Neural Networks

1265_ Implementation analysis of adding tasks to task ready linked list in FreeRTOS

比你想象中更强大的 reduce 以及对敲码的思考

Use the fiddler breakpoint to modify the request parameters and return parameters of an interface, intercept requests, and modify requests and responses
随机推荐
Industrial practice example of industrial defect detection based on openvino deployment
zmq通信
Leetcode 530: minimum absolute difference of binary search tree
IDEA 版 Postman问世,亲测好用
【无标题】416. 分割等和子集
[learn FPGA programming from scratch -16]: quick start chapter - operation steps 2-4- basic syntax of Verilog HDL language description language (both software programmers and hardware engineers can un
MySQL multi table query
Associative array & regular expression
The JS mouse changes the font color and returns to normal
【LeetCode】128. 最长连续序列
What is the difference between encryptors and database encryption products?
iNFTnews | NFT在Web3經濟裏的未來
Introduction to cross platform multimedia rendering engine OPR
Beyond compare 3 key serial number sharing and key revocation solutions
【FPGA】day16-FIFO实现uart协议
投资新手买收益率多少的理财产品合适?
window.open(url)多次打开下载链接被浏览器拦截问题解决方案,js实现循环访问多个下载链接
【LeetCode】338. Bit count
Experimental three character type and its operation (New)
【LeetCode】461. Hamming distance