AXI Bus

AXI Introduction to bus

AXI Bus It's a bus protocol , yes ARM The company put forward AMBA3.0 agreement ( At present AXI4 The published ) The most important part of , It's a high performance 、 High bandwidth 、 Low latency On chip bus . Support misaligned data transmission and burst transmission . In burst transmission, only the first address is required , It also supports simultaneous separate read and write data channels 、 Support significant transmission access and out of order access .

AXI The first two generations of AHB(2.0)、ASB(1.0). among AMBA It also includes a APB Bus , The bus is specially connected IIC、UART And other low bandwidth interfaces .

AXI Several key features of the protocol

1. Read and write address 、 Data separation ;
2. By byte strobe (WSTRB) The implementation supports the function of non aligned data transmission ;
3. When using burst mode , Just transmit the first address and set the burst length ;
4. Read and write data channels are independent , To support low power consumption DMA;
5. Support outstanding function , Multiple addresses can be sent for reading and writing ;
6. Support out-of-order transmission （ That is, out of order transmission ）;
7. It is easy to add register level , In order to achieve timing convergence ;
8. Each channel has a pair of handshake signals ;
9. Both read and write data channels contain a LAST The signal , Used to indicate the last data transmitted by a thing ;

AXI The basic architecture of the bus

AXI Bus 5 Transmission channels

AXI Bus passing 5 Channels for reading and writing , this 5 The channels are ： Read address channel 、 Write address channel 、 Read data channel 、 Write data channel and Write response channel .

• this 5 Each of the two independent channels all Contains a two-way valid and ready Handshake signal .
• The read and write data channels also contain a last The signal , Represents the last data transferred by the transaction .
• The read data channel contains read data and read response signals , The read response signal indicates the completion of the read transaction .
• Write to data channel , Every time 8 Every bit of data will have one byte lane, This signal indicates which... Are on the data bus byte The data is valid ( because AXI Support data transmission with misalignment ); The write response signal indicates that the slave device responds to the write transaction .
• AXI Support disordered transmission , Each transaction will be given a IDtag, The agreement will require the same IDtag All transactions must be completed in an orderly manner , Different IDtag Can be completed in disorder .
  

AXI Bus read / write process

• The master device writes data to the slave device ： First , The main equipment passes through Write address channel Explain the register address to be controlled to the slave device , And some burst modes and control signals ; The main equipment passes through Write data channel Write data to the slave device ; Finally, it passes through the device Write response channel Respond ; Complete data writing to the slave device .

• The master device reads data from the slave device ： First , The main equipment passes through Read address channel Explain the register address and control signal to be controlled to the slave device ; After receiving this information from the device, i , It will read data according to this information ; After these processes , The slave device will pass through Read data channel Send data to the master device .

Signal description

1. Global variables

The signal	Source	describe
ACLK	Clock source	Global reset clock
ARESETn	Master reset signal	Global reset signal , Low level active

2. Write address channel (AW)

The signal	Source	describe	Personal understanding
AWID [3 :0]	host	Write the address ID , That represents the write address signal group IDtag.	It can be associated with just now AXI Support the function of out of sequence transmission
AWADDR[31:0]	host	Write the address .	This is our main data
AWLEN [3 :0]	host	Length of burst write .	AXI Support burst mode , Indicates the number of data in burst mode , The biggest support 16, But the length of each burst requires the signal to be sent to the slave device
AWSIZE[2:0]	host	Burst case size	The data size of each transmission ,2^(AWSIZE), It can be either 1-128 Width
AWBURST[1:0]	host	Type of burst write	Fixed burst reading and writing （00）、 Value added burst read / write （01）、 Packaged burst read / write （10）
AWLOCK[1:0]	host	Lock type	ARLOCK[1:0] or AWLOCK[1:0] To select exclusive access , Use signal RRESP[1:0] or BRESP[1:0] To indicate the success of exclusive access
AWCACHE[3:0]	host	Cache type . This signal indicates the of the transaction bufferable、cacheable、write-through、write-back、allocate attributes Information
AWPROT[2:0]	host	Type of protection	1. Normal access or privileged access ,AWPROT[0]2. Secure access or no secure access ,AWPROT[1] 3. Instruction access or data access ,AWPROT[2]
AWVALID	host	Write address valid .1 Indicates valid , This signal will be maintained , know AWREADY Become high	Personally, I think this signal is also related to AWADDR Sync , Because this signal indicates AWDDR The validity of the data
AWREADY	equipment	Response from device .1 Indicates that the equipment is ready ,0 No preparation number	Indicates that the slave device can receive the address signal , Raising the address should also mean that the address is successfully received ( Or as long as the sign is ready to be pulled up , After a clock cycle, the default receiving from the device is successful )

3. Write data channel

The signal	Source	describe	Personal understanding
WID[3:0]	host	Write IDtag,WID The value of must match AWID The value of matches	Associated with the AXI Support the function of out of sequence transmission ; Need and WID matching , Matching can indicate that the address and data are written to the same slave device
WDATA[31:0]	host	Writing data	The main information of this channel
WSTRB[3:0]	host	Write valve . The interval of the sign is WDATA[(8n)+7:(8n)]	Express WDATA A byte in
WLAST	host	The last data written	When it should be in burst mode, it indicates the last data of the burst
WVALID	host	To write effective ,1 Indicates valid	Indicates that the write data is valid , The write data has been put on the bus
WREADY	equipment	Write ready ,1 Indicates ready	and AWREADY Same thing

4. Write channel response

The signal	Source	describe	Personal understanding
BID[3:0]	equipment	Respond to ID, Must be with AWID matching	It is also to support out of order transmission services ( It's more than that , Because there are usually multiple slave devices )
BRESP[1:0]	equipment	Write response	This signal indicates the status of the transaction . Possible responses ：OKAY、EXOKAY、SLVERR、DECERR
BVALID	equipment	Write response is valid	This explains that I understand AWREADY The tangle of signals , This signal should assist in determining whether the write operation is successful
BREADY	host	Receive response ready ,1 Indicates that the host continues	This signal is used to indicate that the host is ready to receive the signal of the response channel , Feeling is a multi-level feedback signal , To avoid data errors

5. Read address channel

The signal	Source	describe	Personal understanding
ARID [3:0]	host	Read the address ID , Indicates the... Of the read address signal group IDtag.	It can be associated with just now AXI Support the function of out of sequence transmission
ARADDR[31:0]	host	Read the address .	This is our main data
ARLEN [3:0]	host	Length of burst read .	AXI Support burst mode , But the length of each burst requires the signal to be sent to the slave device
ARSIZE[2:0]	host	Size of burst reads	Burst case size
ARBURST[1:0]	host	Types of burst reads	Type of burst write
ARLOCK[1:0]	host	Lock type	ARLOCK[1:0] or AWLOCK[1:0] To select exclusive access , Use signal RRESP[1:0] or BRESP[1:0] To indicate the success of exclusive access
ARCACHE[3:0]	host	Cache type . This signal indicates the of the transaction bufferable、cacheable、write-through、write-back、allocate attributes Information
ARPROT[2:0]	host	Type of protection	1. Normal access or privileged access , ARPROT[0] 2. Secure access or no secure access , ARPROT[1] 3. Instruction access or data access ARPROT[2]
ARVALID	host	The read address is valid .1 Indicates valid , This signal will be maintained , know AWREADY Become high	Personally, I think this signal is also related to ARADDR Sync , Because this signal indicates ARADDR The validity of the data
ARREADY	equipment	Response from device .1 Indicates that the equipment is ready ,0 No preparation number	Indicates that the slave device can receive the address signal , Raising the address should also mean that the address is successfully received ( Or as long as the sign is ready to be pulled up , After a clock cycle, the default receiving from the device is successful )

6. Read data channel

The signal	Source	describe	Personal understanding
RID[3:0]	equipment	read IDtag,WID The value of must match AWID The value of matches	Associated with the AXI Support the function of out of sequence transmission ; Need and WID matching , Matching can indicate that the address and data are read to the same slave device
RDATA[31:0]	equipment	Reading data	The main information of this channel
RRESP[1:0]	equipment	Read response . Indicates the status of the transmission ：OKAY(00)、EXOKAY(01)、SLVERR(10)、DECERR(11)	The write response has a dedicated channel , But the read response is contained in the read data channel
RLAST	equipment	The last data read	When it should be in burst mode, it indicates the last data of the burst
RVALID	equipment	Read effectively ,1 Indicates valid	Indicates that the read data is valid , The read data has been put on the bus
RREADY	host	Read ready ,1 Indicates ready	and ARREADY Same thing

7. Low power interface

The signal	Source	describe	Personal understanding
CSYSREQ	Clock source	System low power request . This signal comes from the system clock controller , Put the peripheral into a low-power state	Low power signal
CSYSACK	Peripherals	Low power request response
CACTIVE	Peripherals	clock active.1 Indicates a peripheral clock request
CSYSREQ	Clock source	System low power request . This signal comes from the system clock controller , Put the peripheral into a low-power state	Low power signal
CSYSACK	Peripherals	Low power request response
CACTIVE	Peripherals	clock active.1 Indicates a peripheral clock request