Mastering JESD204B (2) – Debugging of AD6676

Configuration Section

Clock chip HMC7044 configuration

HMC7044 Chip Description

HMC7044 chip block diagram:

The chip used in this projectThe mode is external clock (input 100MHz crystal oscillator), PLL1 is enabled mode, and the VCO frequency is 2400MHz; the clock configuration relationship is as follows:
a) The clocks input to AD are configured as VCO divided by 12 frequency 200MHz;
b)The SYS_REF input to AD is configured as VCO divided by 1024 to 2.34375MHz;
c) The clock input to FPGA is configured as 100MHz;
d) The SYS_REF input to FPGA is configured as 2.34375MHz;
e) The GTX clock input to the FPGA is configured as 200MHz (the reference clock for GTX);

HMC7044 register part configuration:

SPI configuration timing:

AD chip AD6676

AD6676 block diagram:

a) Signal bandwidth: 20 MHz to160 MHz;
b) IF center frequency: 70 MHz to 450 MHz;
c) 2.0 GSPS to 3.2 GSPS ADC clock rate;
d) Selectable decimation factors: 12, 16, 24 and 32;
e) The on-chip attenuator has a range of 27 dB and a step of 1 dB;

ADC configuration:

SPI configuration timing:

JESD204B Interface Configuration

JESD PHY Configuration

Line rate: 4Gbps;
Reference clock: 200MHz;
PLL TYPE: CPLL;

JESD Configuration

Data receiving section

After the configuration is completed, wait for the link of the link. The linking process of the link mainly includes the following steps:
JESD204B link establishment
AD6676 JESD204B Tx interface according to the provisions of JEDEC standard 204B (July 2011 specification), works as Subclass 0 or Subclass 1.The link establishment process
is divided into the following steps: code group synchronization, ILAS and user data.
Code Group Synchronization (CGS) and SYNCINB
Code Group Synchronization (CGS) is the process by which a JESD204B receiver finds the boundaries between 10-bit symbols in a data stream.During the CGS phase, the JESD204B transmit (JESD Tx) module transmits the /K28.5/ character.The receiver must use clock and data recovery (CDR) techniques to locate /K28.5/ characters in the incoming data stream.The receiver issues a synchronization request by asserting a low signal on the AD6676 SYNCINB± pins.Then, JESD Tx starts sending /K/ characters.After the receiver is synchronized, the SYNCINB signal is deasserted and brought high.The AD6676 then sends an ILAS at the next LMFC boundary.SYNCINB± pin operation options can be controlled through SPI registers.Although the SYNCINB input is configured by default as a CMOS logic level on the positive pin, it can also be configured as a differential LVDS input signal on the positive/negative pin through Register 0x1E7.The polarity of the SYNCINB input signal can also be reversed using Register 0x1E4.

Data Receive:

Note:
The hardware block diagram refers to the previous article ""Mastering JESD204B (1)-AD6676 debugging;