pg_memory_barrier_impl in Postgresql and C's volatile

pg_memory_barrier_impl in PG

The definition of memory barrier in arch-x86.h:

#define pg_memory_barrier_impl() \__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory", "cc")#endif

Copy

What does

lock;addl mean?

• All write operations after the lock will cause bus synchronization, that is, the cpu store buffer will be flushed out, and the cachelines corresponding to other CPUs will be invalidated through the modified address.
• Then this addl adds 0 to the rsp register (the rsp stack pointer points to volatile data, and you need to use rsp to find the variable in memory) Although it will not change the value of rsp, it will trigger the flush action of the store buffer, and thenSync cacheline data across all cores.
• The final effect is that the cacheline is all synchronized once, and the old value will not be read.

C's volatile

When the value modified by volatile is modified, the variable will not be loaded into the register by the compiler; if it is not modified, the CPU may read from the register or from the memory, and the results of concurrent reading on both sides may beinconsistent.

(java's volatile may have its own asm(lock;addr) function, there are differences here)

Difference

volatile prevents the compiler from stuffing the variable into the register. If it goes into the register, the value of the register will be taken directly when reading, and the stroe buffer and cache will not be taken at all, and the memory_barrier synchronization of the cacheline data will have no effect.