当前位置:网站首页>Conversion of fixed-point number to floating-point number of vivado IP core
Conversion of fixed-point number to floating-point number of vivado IP core
2022-07-29 06:38:00 【Doze in the wind】
Vivado IP The fixed-point number of the core is converted to a floating-point number Floating-point
Catalog
One 、 What is a fixed-point number ?
Two 、 What is a floating point number ?
3、 ... and 、Floating-point IP Core configuration steps
5、 ... and 、 Simulation analysis
Preface
With the continuous development of manufacturing technology , Field programmable logic gate array (FPGA) More and more integration , More and more applications , Among them, some mathematical processing classes must be used when processing digital signals IP nucleus . Recently, research on Spatial Adaptive Anti-jamming Technology is under way FPGA Hardware implementation , Some of them are inevitably used IP nucleus , Today, let's introduce in detail from fixed-point number to floating-point number vivado In the middle of Floating-point This IP Nuclear bar , I hope it can help you in your study .
Tips : The following is the main body of this article , All are original by the author , It's not easy to write an article , I hope you will attach a link to this article when reprinting .
One 、 What is a fixed-point number ?
Fixed-point number : The decimal position is fixed The number of is called fixed-point number , That is, the decimal point is a number fixed at a certain position . Fixed point numbers are divided into fixed-point integers and fixed-point decimals , Among them, fixed-point integers are divided into signed fixed-point integers and unsigned fixed-point integers , Fixed point decimals are divided into signed fixed-point decimals and unsigned fixed-point decimals . This article focuses on 32 position (1+1+30) Signed fixed-point decimal , The size of digits can be set according to different usage scenarios , The other three categories are relatively simple , I won't introduce it here .
The position of the decimal point is fixed before the most significant digit 、 After the sign bit , Pictured 1 Shown . The decimal point position of fixed-point decimals is implicitly agreed , The decimal point does not really need to occupy a bit position .

In the figure 1 in ,
Symbol bit , When
=0 when , Is a positive decimal ; When
=1 when , Decimals are negative decimals .n Is the decimal bit width , The width of decimal places will directly affect the accuracy of decimal , A wide n The larger the, the higher the precision .
stay xilinx vivado Medium IP nucleus , Signed fixed-point numbers are represented by complements , So we must understand the original code 、 Inverse code 、 The relationship among complement . The original code of a positive number 、 Inverse code 、 The complement is the same ; The original code of a negative number is the original code of a positive number after taking the absolute value , Reverse the negative original code bit by bit , That is, we get the inverse code of negative numbers , The negative complement is obtained by adding one to the negative inverse .
Okay , Don't talk much , Direct example .
example1: Suppose a signed 32 position (1 Bit sign bit +1 Bit integer +30 A decimal place ) Fixed point decimals are expressed in binary 32'b0011_0111_0110_1100_1111_0101_1101_0000, So what is the decimal system instead of the decimal system ? First , Its sign bit is 0, It is known that it is a positive number , So the original code 、 Inverse code 、 The complement is the same ; secondly , The integer bit is 0, The actual corresponding integer bit is also 0; then , Its 30 The decimal part is 30'b11_0111_0110_1100_1111_0101_1101_0000, Convert to decimal number, that is 929887696; Last , We know when 30 All decimal places are 1 The decimal number represented by hour is 1073741823, So by the 929887696/1073741823≈0.8660254 It can be concluded that the fixed-point decimal is reduced to a real number, which is approximately 0.8660254.
example2: Suppose a signed 32 position (1 Bit sign bit +1 Bit integer +30 A decimal place ) Fixed point decimals are expressed in binary 32'b1100_1000_1001_0011_0000_1010_0011_0000, So what is the decimal system instead of the decimal system ? First , Its sign bit is 1, We can see that it is a negative number , that 32'b1100_1000_1001_0011_0000_1010_0011_0000 Indicates its complement , The negative original code is different from the complement , We should find out the original code first , Its original code is 32'b0011_0111_0110_1100_1111_0101_1101_0000; secondly , The integer bit is 0, The actual corresponding integer bit is also 0; According to the previous analysis, the positive decimal represented by this code is approximately 0.8660254, So far, it can be concluded that the fixed-point decimal into a real number is approximately -0.8660254.
Two 、 What is a floating point number ?
Floating point numbers are a standardized expression , The common standard is IEEE754 standard , Used to approximate real numbers , And we can make a trade-off between the expression range and the expression accuracy , So it is called floating point number .( About IEEE754 Standards do not understand their own Baidu , I'm not going to repeat it here ).
example3: Suppose a signed 32 Bit floating point ( The single precision is 32 position , The double precision is 64 position ) In binary 32'b0011_1111_0101_1101_1011_0011_1101_0111, So according to IEEE754 According to the standard, the sign bit is 0, It means positive decimal , The index part is 8'b0111_1110, The decimal part is 23'b101_1101_1011_0011_1101_0111, according to IEEE754 According to the standard, the decimal number it represents is 0.8660254.
example4: Suppose a signed 32 Bit floating point ( The single precision is 32 position , The double precision is 64 position ) In binary 32'b1011_1111_0101_1101_1011_0011_1101_0111, So according to IEEE754 According to the standard, the sign bit is 1, Means negative decimal , The index part is 8'b0111_1110, The decimal part is 23'b101_1101_1011_0011_1101_0111, according to IEEE754 According to the standard, the decimal number it represents is -0.8660254.
3、 ... and 、Floating-point IP Core configuration steps
stay vivado Mid search Floating-point, To find the IP After the core, you can complete the corresponding configuration according to the following operations .
1. First configuration Operation Selection Interface , Pictured 2 Shown .

2. Next configuration Precision of Inputs Interface , Pictured 3 Shown .

3. Then configure Precision of Result Interface , Pictured 4 Shown .

4. Then configure Optimizations Interface , Pictured 5 Shown .

5. Final configuration Interface Options Interface , Pictured 6 Shown .

above 5 After all the interfaces are configured, you can click on the lower right corner OK Button generation IP nucleus .
Four 、 Simulation
1. Top level code
Build a top-level module , Name it fix_to_float_top, Used to instantiate the just generated IP nucleus .
The code is as follows :
`timescale 1ns / 1ps
//
// Company: Chongqing University
// Engineer: CLG
// Create Date: 2022/07/22 09:37:43
// Design Name:
// Module Name: fix_to_float_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
module fix_to_float_top(
input clk,
input s_axis_a_tvalid, // Input data valid flag signal
input [31:0] s_axis_a_tdata, // Input Fixed-point number data
output m_axis_result_tvalid, // Output data valid flag signal
output [31:0] m_axis_result_tdata // Output float data
);
floating_point_ip u1_floating_point_ip(
.aclk(clk),
.s_axis_a_tvalid(s_axis_a_tvalid),
.s_axis_a_tdata(s_axis_a_tdata),
.m_axis_result_tvalid(m_axis_result_tvalid),
.m_axis_result_tdata(m_axis_result_tdata)
);
endmodule
2. Simulation code
Build a simulation module , Name it fix_to_float_tb, It is used to simulate the instantiation of the top-level module just now IP nucleus .
The code is as follows :
`timescale 1ns / 1ps
//
// Company: Chongqing University
// Engineer: CLG
// Create Date: 2022/07/22 10:02:05
// Design Name:
// Module Name: fix_to_float_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
module fix_to_float_tb( );
reg clk;
reg a_valid_a = 1'b0;
reg [31:0] a_a = 32'b0;
wire [31:0] result_a;
fix_to_float_top u1_fix_to_float_top(
.clk(clk),
.s_axis_a_tdata(a_a),
.s_axis_a_tvalid(a_valid_a),
.m_axis_result_tdata(result_a),
.m_axis_result_tvalid(m_axis_result_tvalid)
);
always #5 clk=~clk;
initial begin
clk = 1'b0;
#100;
a_valid_a <= 1'b1;
a_a <= 32'h376CF5D0;
#500;
a_valid_a <= 1'b1;
a_a <= 32'hc8930a30;
end
always @(posedge clk) begin
if (m_axis_result_tvalid == 1'b1) begin
a_valid_a <= 1'b0;
end
end
endmodule
5、 ... and 、 Simulation analysis
The simulation results are shown in the figure 7 Shown , Compare the fixed points listed above 、 Examples of floating point numbers , It can be seen that this module successfully converts fixed-point numbers into floating-point numbers .

summary
This time, I introduce Fixed-point number 、 Floating point numbers and how to use vivado Medium Floating-point IP The core converts fixed-point numbers 32 Bit floating point .
边栏推荐
猜你喜欢

自动化测试的生命周期是什么?

五、 无线通信网

虹科分享 | 带你全面认识“CAN总线错误”(二)——CAN错误类型

day14_ Unit test & Date common class & String common class

虹科分享 | 带你全面了解“CAN总线错误”(四)——在实践中生产和记录CAN错误

Redshift restore SP effect - SP map export settings and map import configuration

浅谈缺陷描写样式

虹科 | 使用JESD204串行接口高速桥接模拟和数字世界

day13_ Under multithreading

虹科Automation softPLC | MoDK运行环境与搭建步骤(1)——运行环境简介
随机推荐
DDoS攻击与CC攻击的区别
Use of for statement in Verilog
Vivado IP核之RAM Block Memery Generator
Explain the difference between FIR filter and IIR filter in detail
Common server faults and their solutions
FPGA - odd even frequency division and decimal frequency division code routine
网络安全学习(二)
虹科Automation softPLC | 虹科KPA MoDK运行环境与搭建步骤(2)——MoDK运行环境搭建
Merkletree builds QT implementation UI
Six common ways for hackers to attack servers
Phishing mail disposal
网站受DDoS攻击的表现以及查看方法
使用STP生成树协议解决网络中的二层环路问题
Arrays&Object&System&Math&Random&包装类
基于FPGA的IIR型滤波器设计
软件测试的优势有哪些?看看你了解多少.....
FPGA—奇偶数分频和小数分频代码例程
day03_1_流程控制
DDoS details
七、 下一代互联网IPV6