Verilog implements a divide-by-9 with a duty cycle of 5/18

Design ideas:
Set up a rising edge-triggered counter and a falling edge-triggered counter, whose duty cycle is both 6/18 and divided by 9, then these twoThe clocks are differences in phase by half a cycle, if they are summed, according to the nature of the sum, the result should be a duty cycle of 6/18-1/18=5/A divide-by-9 clock of 18.
or
Set up a counter triggered by rising edge and falling edge respectively, its duty cycle is 4/18 and divided by 9, if the two clocks are phase or, the result should be a divide-by-9 clock with a duty cycle of 4/18+1/18=5/18.

Code Implementation

Design section

`timescale 1ns/1nsmodule clk_divider //5/18 divider( input clk_in,input rst_n,output clk_out);