Design of direct spread spectrum communication system based on FPGA (with main code)

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Today, we bring you direct spread spectrum communication , Because of the long space , It is divided into three parts . Today, I will bring the next article , It's also the last one , Simulation , Don't talk much , Loading .

Here are also the hyperlinks to the first two articles ：

Direct spread spectrum communication （ On ） Theoretical basis

Direct spread spectrum communication （ in ）Verilog Realization

Reading guide

This chapter is applicable to the great Xia who has a certain communication foundation , The theory used in this paper is not only spread spectrum communication . In order to facilitate learning , This chapter will be in a practical way , Simulation of the whole project . And some key simulation results are explained . You can read according to your own needs , Reference learning .

Part three content summary ： This chapter will introduce the simulation design of the system .

Simulation

One 、 The establishment of modules and the generation of simulation environment

1.1、 On the computer , Find a directory without Chinese characters , Create the following files , Pictured 6：

chart 6

The above figure shows the files that can be created ,sim_wave.do It is a simulation waveform saving file .tt.do.

The code is as follows ：

# establish  library  be known as ”work”
vlib work
vmap work work
# Compile the current directory (./) Medium  top.v、mcu.v …. 
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./top.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./mcu.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./slaver.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./coder.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./add_noise.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./decoder.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./correct.v
vlog -work work -L mtiAvm -L mtiOvm -L mtiUPF ./Correct_Decoder.v
# Simulation  work  Medium  top  Model 
vsim -novopt work.top

The above is the input mode for simulation , It can also be simulated directly in a graphical way . But I didn't start the simulation , Because we need to add a statement below . But no response file .

tt.bat The code for is as follows ：

echo
pause
vsim -do .\tt.do
pause

tt.bat The file is a batch file , Just open modelsim、 function tt.do Files use . You can also not use this file ( Not described in detail below ).

1.2、 Write the corresponding code to the corresponding file (sim_wave.do、tt.bat Files can be ignored ).

1.3、 use modelsim Open by top.v file ( Or you open it first modelsim, Then change the directory to the directory mentioned above ). The running interface is shown in the figure 7(modelsim6.5d)：

chart 7

The garbled code in the figure is modelsim Not compatible with what I am using notepad Chinese characters written by the software , Great Xia, you can ignore me .

1.4、 stay Transcript Input in ”do tt.do”, Run... In the current directory tt.do file .

In operation , Finally, jump out as shown in the figure 8 The window of . If there is an error , Will be in Transcript Use red font to explain ( Of course , It's all in English ).

chart 8

In block diagram 1 Is the model of the whole simulation platform , You can click on the model + an . block diagram 2 Displays the items contained in the current model .

1.5、 Add waveform , Pictured 9、10、11, For modules coder Add waveform , And the waveforms are grouped .

chart 9

chart 10

chart 11

Add waveforms to all simulation models , And grouping , Pictured 12.

chart 12

chart 13

1.6、 Simulation starts

stay Transcript Input in ”run -all” Wait for the result . The above will generate the whole process of simulation environment . Each module will be described below .

Two 、 Module simulation

2.1、 modular mcu Simulation

mcu Act as a source generation module , Its waveform is as shown in Figure 14.

chart 14

stay send_ena When enabled , When insourse_ena For the high time , Data from indatabyte The first 7 Bit port output to coder modular , Send hexadecimal in the figure 24 The process of , Only in insourse_ena Send for high . The module also generates two clocks , The two clocks are 31 Times the frequency .clk1 and clk31.

2.2、 modular coder Simulation

modular coder Will be right mcu The transmitted data is encoded 、 Spread spectrum . The simulation waveform is shown in the figure 15.

chart 15

In the picture in_data_buf Is the sending code , When receiving send_ena after , Send the header and data frame first , Then send the data from... As shown in the figure 133600us Start sending data ”0010”( Hexadecimal 2) And then send the supervision code ”101”, stay 177000us Start sending data ”0100”( Hexadecimal 4) Then send the supervision code ”110”. After all the data has been channel encoded ,out_data Send out .

2.3、 modular noise Simulation

Add interference , the coder Sent 2bit Data extends to 3bit data , And add to the noise .

The simulation waveform is shown in the figure 16.

chart 16

The picture is right 1bit After spreading the data , among un_noised_data For input data ( Noiseless )、 Process and noise Add up the data , Get data noised_data.

This module acts as an additive interference source in the channel .

2.4、 modular decoder Simulation

Despreading is the design focus of this system . It includes synchronization of synchronization header and data receiving, etc .

This design uses a cyclic pseudo-random as the despreading code . Use a 31bit The register of , Initialize to a series of 5 Of m Sequence , End to end cycle . that , Take a number on each bit of the register , Can get a pseudo-random sequence . Come to the conclusion that 31 individual m Sequence . And close to the register bit , Collected m The sequence has only one bit shift . therefore , This method can be used , Data sent at the sending end , No matter when it is sent , stay 31bit In registers 1 Corresponding to... In registers . More popular , No matter when the sending device starts sending . Can be in 31bit Found a register in the register of m The sequence corresponds to .

Because in 31 It is more expensive to collect data from bit registers at the same time FPGA Internal resources , Therefore, this design uses each of the registers 10 individual bit Bit by bit . If the former 10 Failed to find the corresponding m Sequence , Then add to the later 10 individual , And so on , stay 3 In the accumulation of times , Always scan completely 31bit Bit register . At this point, the corresponding bit can be found .

Because the data header of the sending device is 10 individual ”1” and 1 individual ”0”, And in the 10 individual ”1” Medium 1 It is an extension , There is no way to directly get adjacent ”1” At the junction of , And in getting the right m After the sequence bit , Must be synchronized , The method of synchronization is to collect the last ”0” As synchronization .

After receiving the completed data header , Perform data frame synchronization . The data frame is 4bit data ”0000” and 3bit Supervision position ”000”.

After receiving the completed data frame, the data is started . Because of the big data , The cumulative cardinality here is 100, The threshold is 30, that , When receiving 130, Indicates that a ”1”.

The simulation results are as follows ：

chart 17

chart 17 Is the overall working state of the receiving ,sum1~sum10 Collect separately 10 Register bits , When there is 1 Received more than 130, This indicates that the register should be on m The sequence can receive 1 individual ”1”,sum It is the de spread statistics of data frames and data .

chart 18

chart 18 It is a complete data despreading process ,clk31 Is the acquisition clock , The data is in_data_buf, From input to output , After a period of delay, it is transmitted to the despreading module .psumi Is the value of the despreading , Add up to get sum(in_data[2] Judge . by 1, Then add ; by 0, Then subtract ). If sum exceed 130, It indicates that the sending data is ”1”, Otherwise ”0”.( The above is the data ”1” Example )

By despreading the data , Deliver to correct Module for error correction .

2.5、 modular correct Simulation

modular correct Error correction module . It analyzes the despread data , That is, the inverse operation of Hamming code . The simulation process of this module is omitted .

2.6、 modular Slaver Simulation

Slaver It is the receiving module end , It will expand 、 The corrected data is stored . The simulation process is omitted .

2.7、 modular Top Simulation

Top The module should be explained first , Because it is a simulation platform , Its sub modules include mcu and slaver. It counts the sending and receiving of the two modules 、 And calculate 、 Output , And set the module parameters . The following settings send data bits as 500 Output result of ( chart 19、 chart 20)：

chart 19

chart 20

The above is the simulation process of the whole design .

This is the end of this article , This is the end of direct spread spectrum communication , Great Xia , I'll see you again ！ END

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