FIFO implementation with single port RAM

RAM classification

RAM According to the number of ports , Can be divided into

Single port RAM

Single port RAM There is only one set of data lines and one set of address lines , There is only one clock , Read and write the common address line . The output has only one port .
So single port RAM The read and write operations of cannot be performed at the same time . When wea When pulling high , The data will be written to the corresponding address , meanwhile douta The output data is consistent with the data written at this time , Therefore, it is necessary to regenerate the corresponding read address to addra, also disable fall wea.

Fake double mouth RAM

The input has a set of data lines , Two sets of address lines , Two clocks .
therefore A port is read-only , The other port only writes , But the clock for writing and reading can be different , And the bit width ratio may not be 1:1. That is, it is allowed to write A Simultaneous reading of B, And the rate can be different .

What a double mouth RAM

The input has two groups of address lines and two groups of data lines , Two clocks .
The output has two separate data lines .
So double port RAM Both ports have read and write ports respectively , You can read and write without interference , Don't interfere with each other .