Digital integrated circuit: MOS tube device chapter (II)

Digital integrated circuit ：MOS Tube device chapter （ Two ）

We know ,RC Parameters are the main factors that determine the delay characteristics of a gate circuit , about MOS Tube speaking , Under the switch model , resistance R Basically, it can be regarded as a constant on resistance Ron, And for capacitance C, You need to model and analyze the specific values of different workspaces , This article mainly analyzes MOS The capacitance of the tube .
MOS The capacitance of the tube mainly comes from the gate capacitance of the gate to the source drain and the substrate ; It also comes from the junction capacitance of the source and drain , As shown in the figure below .

Gate capacitance

Influence of capacitance per unit area and aspect ratio

The capacitance per unit area of the grid is inversely proportional to the thickness of the grid , The total capacitance of the grid is proportional to the width and length of the channel , Because in the process , The length of the channel is a fixed minimum feature size , Therefore, in customized design , The main parameter that affects the gate capacitance is the channel width W.

Overlapping capacitance

During annealing, the highly doped region of source and drain turns to the low doped region （ substrate ） The spread of , In fact, the effective conductive channel is shorter , Source pole , There is overlap between drain and grid , The parallel plates produced by this part of overlap will produce a part of parasitic capacitance .

Gate capacitance in different working areas

When the cut-off zone , The grid capacitance mainly comes from the oxide layer of the grid , And because the source and drain have not yet formed a conductive channel , So if you ignore overlap Outside the capacitance of , It can be considered that the grid is right S and D There is no capacitance , The capacitance of the grid is all on the substrate bulk. With Vgs Grow slowly , And less than VT front , The depletion layer will continue to thicken , Because the capacitance is inversely proportional to the dielectric thickness , Depletion layer capacitance decreases , In addition, the capacitance formed by the depletion layer is in series with the gate oxide capacitance , The series connection between capacitors will reduce the total capacitance , This makes the gate capacitance increase with Vgs Increase and slowly decrease .
When Vgs increase >VT when , Inversion layer formation , Communication D and S, And the gate and the substrate are isolated , therefore Cgb=0, The gate oxide capacitor turns to S and D Flat stall , Linear area ,D,S It's symmetrical , So the grid is right S and D Average capacitance .
With VDS increase ,D The polar conductive channel narrows or even breaks , Enter the saturation zone ,Cgd It also decreases gradually until 0, and Cgs Gradually increase , Finally, it rises to 2/3Cg, In general , In saturated zone , The grid capacitance is decreasing .

The above process can be summarized by the following pictures , The picture on the left is Vds=0 Increase when Vgs, It is equivalent to from the cut-off area to the linear area , And because Vds=0, The source and drain are symmetrical , Half of the grid capacitance of each component ; The picture on the right is Vds Gradually increase , Tend to saturation , Total grid capacitance , Change of capacitance of source and drain stages , The source capacitance keeps increasing until 2/3 Total capacitance of , The drain capacitance keeps decreasing .

Summary