General multiplier design, verilog code

One 、 Preface ：

        verilog Is a language for describing hardware , Using the multiplier compiler directly will optimize the multiplier IP.

         Small bit width , One cycle can output results , Large bit width allows you to select pipelined output . But the multiplier IP There are also restrictions , Bit width limit , Unknown timing, etc .

        The commonly used multiplication method is shift addition . for example

A = A<<1 ;       // complete A * 2
A = (A<<1) + A ;   // Corresponding A * 3
A = (A<<3) + (A<<2) + (A<<1) + A ; // Corresponding A * 15

        A shift register and an adder can be used to multiply 3 operation , But multiply by 15 You need to use 3 Shift registers and 3 An adder , Reverse thinking can also use shift subtraction . Be careful ： Sometimes a digital circuit cannot add multiple variables in one cycle , Multiple addition will cause the timing to be unsatisfied . here , Pipelined multipliers are effective .

Two 、 principle ： It's like the decimal system

The multiplicand corresponds to the multiplier bit Bits are shifted and accumulated , Even if the multiplication process is completed . Suppose a clock cycle can only complete one accumulation , Then the least multiplication time is exactly the bit width of the multiplier , It is recommended to use the number with narrow bit width as a multiplier .

3、 ... and 、verilog Design

module    mult_low
    #(parameter N=4,
      parameter M=4)
     (