Introduction to FPGA (I) - the first FPGA project

Verilog Code writing and related grammar

test.v

//  The module name is consistent with the file name 
module test(       
		input				port_a				, //  Only wire, No, reg, Default wire
		input				port_b				, 
		input				port_c				, 
		output	wire		port_d				, //  Default wire（ conductor ）, Also have reg（ register ） 
		output	wire		port_e				,
		output	wire		port_f				,
		output	wire		port_g				,
		output	wire		port_h				
);                 

// assign ： Yes wire Type 
// always ： Yes reg  Type 

assign port_d	=		port_a & port_b;	//  Bitwise AND 
assign port_e	=		port_a | port_c;    //  Press bit or 
assign port_f	=		~port_a;            //  Bitwise non 
assign port_g	=		port_b ^ port_c;    //  Exclusive or 
assign port_h	=		port_a ^~ port_c;   //  Same as or 

endmodule

tb_test.v

 // `timescale 1ns/1ps //  Time unit  /  Time precision （ Similar to the scale , Company cm, precision ms）
 `timescale		1ns / 1ns           //  Time precision can also be equal to time units 
 
 module tb_test;                    //  The test module has no input and output ports 
 
 //  Three wires of the signal source 
 reg			test_a;
 reg 			test_b;
 reg 			test_c;
 //  Connect the five wires of the oscilloscope 
 wire			rslt_d;
 wire			rslt_e;
 wire			rslt_f;
 wire			rslt_g;
 wire			rslt_h;
 
 // initial  Assigned signal , Must be defined as reg type 
 initial begin
		test_a	=			1;  	//  stay 0 Time gives initial value 
		test_b	=			0;  	
		test_c	=			1;	
		#5							//  Time delay 5ns
		test_a	=			0;  	
		test_b	=			1;  	
		test_c	=			1;			
		#5							
		test_a	=			0;  	
		test_b	=			0;  	
		test_c	=			0;	
 end
 
 //  Modularization （ Similar to function call ）
 test			test_inst(       
		.port_a					(test_a), 
		.port_b					(test_b), 
		.port_c					(test_c), 
		.port_d					(rslt_d),   
		.port_e					(rslt_e),
		.port_f					(rslt_f),
		.port_g					(rslt_g),
		.port_h					(rslt_h)
); 
 
 endmodule

Modelsim Simulation steps

• First step ： New project .
  
• The second step ： Specify the project name and save path , The rest remain unchanged by default .
  • Project Name：aaa
  • Project Location：./sim
    
• The third step ： Add an existing file test.v and tb_test.v.
  
  
• Step four ： Compile the added file .
  
  • After successful compilation , You can see the file status Turn to green check .
    
    The prompt message is displayed successfully .
    
• Step five ： Switch to Library Next , find work file , Click on + Number , Find out test and tb_test file .
  
  
• Step six ： Yes tb_test File start simulation , Right click on the file ,Simulate without Optimization
  
• Step seven ： Pop up sim Window , You can see the name of the instantiated module
  
• Step eight ： stay tb_test Right click to add Wave, stay test_inst Right click to add Wave.
  
  
• Step nine ： take Wave The window is displayed independently , Click the following icon in the default layout .
  
• Step 10 ：Wave Left side of window , Test ports and module ports have been shown in the form of a list .
  
  • Click on the icon in the lower left corner , Don't show paths , More concise
    
    
• Step 11 ： Smart grouping ,Ctrl + A,Ctrl + G.
  
• The twelfth step ： Modify the running time , Click on Run
  
  
• Thirteenth Step ： Click on Run after , The waveform is not obvious , Click global preview
  
  • Zoom in at the cursor
    
• The fourteenth step ： Check whether the waveform is correct , So as to check whether the code logic is correct .