Clock distribution of jesd204 IP core (ultrascale Series)

ultrascale series FPGA Clock allocation for

JESD204 need 5 Seed clock , Respectively ：

1、 Clock of transceiver refclk,

2、 Kernel clock core_clk, The core clock rate is a single lane Transmission rate 1/40,

3、AXI Bus clock s_axi_aclk,

4、 Configure the clock dynamically drpclk,

5、 Deterministic delay sysref, The clock and core_clk Must be homologous .sysref Rate is ：  Lane_rate/(10*F*K)/2^N;N As a positive integer .

          The clock network can be allocated by the clock network diagram below ,refclk after IBUFDS_GT Then it is divided into two ways , All the way to the transceiver , All the way through BUFG_GT Send to nuclear clock . after BUFG_GT The later clock can be used as the user clock . You can use this clock to divide the frequency to get sysref.

        s_axi_aclk And drpclk No specific requirements , It can be used FPGA Clock frequency division of the clock gets , You can also use the nuclear clock to divide the frequency .

The concrete implementation is realized by the primitive .

// Clock distribution 

    IBUFDS_GTE3 CPLL_CLK (
        .I      (refclk_p               )   ,
        .IB     (refclk_n               )   ,
        .CEB    (1'b0                   )   ,
        .O      (refclk                 )   ,  // As the clock of transceiver 
        .ODIV2  (refclk_1               )      // after BUFG_GT After as /core_clk
    );

    BUFG_GT refclk_bufg_gt_i  (
        .I       (refclk_1      )   ,
        .CE      (1'b1          )   ,
        .CEMASK  (1'b0          )   ,
        .CLR     (1'b0          )   ,
        .CLRMASK (1'b0          )   ,
        .DIV     (3'b000        )   ,
        .O       (refclk_2      )       //core_clk
    );

    refclk_wiz  u_refclk_wiz(
        .clk_160    (core_clk       )   ,     // output clk_160
        .clk_100    (clk_100_ref    )   ,     // output clk_100
        .reset      (reset          )   , // input reset
        .locked     (locked_ref     )   ,       // output locked
        .clk_in1    (refclk_2       )        //input  160MHz
    );      // input clk_in1 

after BUFG_GT After the clock can be used IP The core divides the frequency to get the clock we need .

ultrascale series FPGA : GTH The location of

       about ultrascale Series configuration JESD204 PHY You need to select the position of the transceiver , Can pass UltraScale FPGAs Transceivers Wizard This IP Check , see physical resources Of channel, Check the corresponding... Of the transceiver BANK, Through the schematic BANK Select the position of the transceiver .

about GTH, Four transceivers form a Qaud, One Qaud There are four in it CPLL、 One QPLL1、 One QPLL0.