[Verilog basics] summary of some concepts about clock signals (clock setup/hold, clock tree, clock skew, clock latency, clock transition..)

• setup time： trigger （DFF） The rising edge of the clock comes Before , The minimum time gap for data to remain stable is the establishment time .

• hold time： trigger （DFF） The rising edge of the clock comes after , The minimum time gap for data to remain stable is the holding time .

• clock skew： because Path delay , The time difference between the arrival of the same clock signal in two different registers , According to the difference, it can be divided into positive offset and negative offset .

The time difference between the clock tree reaching different endpoints .

• clock jitter： refer to The change of the clock cycle . The difference between two clock cycles , This error is at