Aurora8b10b IP use-04-ip routine application example

Preface

This article mainly introduces about Aurora8B10B IP Use of officially provided formwork works , A brief simulation is carried out to check the test results , Ensure the correctness of simulation transmission .

Example design architecture

Example design Every Aurora 8B/10B The kernel contains a sample design （< Component name >_exdes）, The design uses the kernel in a simple data transmission system .
The sample design contains the following components ：

• Connect to TX Interface frame generator (FRAME_GEN)
• Connect to RX User interface frame checker (FRAME_CHECK)
• For debugging and testing VIO/ILA example

The following figure shows an example design block diagram of a full duplex kernel .

The example design uses all the core interfaces . No, TX or RX The simplex kernel of the interface has no FRAME_GEN or FRAME_CHECK block .

Sample code structure

The code structure of the example project is as follows ：

1. Contains a Aurora IP modular , This module contains and Aurora Drivers and settings related to kernel configuration operations .
2. The two interfaces are interchangeable with each other ：LL turn AXI and AXI turn LL Interface module .

FRAME_GEN modular

FRAME_GEN The module follows AXI4-Stream The agreement is for each PDU、UFC and NFC Interface generates user traffic . This module contains a pseudo-random number generator , It uses a linear feedback shift register with a specific initial value (LFSR) To generate predictable data sequences . FRAME_CHECK The module uses this data sequence to verify Aurora Integrity of data channels . The module input is user_clk、reset and channel_up.LFSR Used to generate pseudo-random data ,LFSR The lower order of is connected to REM Bus .

Interface description

The interface is similar here AXI Bus , The official estimate is to reuse the previously written modules , Therefore, this part of the bus name has not been modified or rewritten . The following table gives a brief description of the interface .

User Interface	describe
TX_D	Data interface , Same as s_axi_tx_tdata.
TX_REM	REM The meaning here should be remaining, Its output is connected to the next module LL_IP_REM Interface , According to its numerical value TKKP by 10 or 11, Yes, the postpartum data are more random .
TX_SOF_N	start of frame, Frame start signal , Low efficiency
TX_EOF_N	end of frame,, Low efficiency , Same as s_axi_tx_tlast
TX_SRC_RDY_N	Source ready signal , Low efficiency ,s_axi_tx_tvalid
TX_DST_RDY_N	Destination ready signal , Low efficiency ,s_axi_tx_tready

System Interface	describe
USER_CLK	The clock
RESET	Reset
CHANNEL_UP	passageway link Identification signal

For code explanation, please refer to the following ：

Aurora IP A brief analysis of nuclear examples

stay FRAME_GEN The control transmission in the module is controlled by a state machine , After reading the code , Extract the code state machine part , Draw the state transition diagram of the module .

FRAME_CHECK modular

FRAME_CHECK Module validation RX Data integrity . This module is used with FRAME_GEN The modules are the same LFSR And the initial value to generate the expected RX The frame data . Compare the received user data with the locally generated stream , And according to AXI4-Stream The agreement reports any errors . FRAME_CHECK The module is suitable for PDU、UFC and NFC Interface .

Routine based on the generated linetype LFSR, adopt REM The identification of the bus is decoded to recover the transmitted pseudo-random data .

Create frame mode project

Build a new empty project , Select a chip with high-speed serial port , And then in IP Select under directory Aurora IP, If you just view the simulation and keep the default configuration . Select this IP Right click , Open the template project , A new template project will be automatically created after confirmation .

After the establishment, you can see that the code structure in the routine is the same as that described above .

View simulation

Select the simulation button and click Run behavior level simulation .

In simulation design , The routine calls two Aurora IP Carry out transceiver loop test . Send and receive data are the same data . Add any call instantiated IP Signal to waveform window , Then click Run and wait . After waiting for a while , stay rx and tx_data The signal can be seen to send and receive signals , Here's the picture , The receiving and transmitting signals consist of more than a dozen clk Time delay of , At the same time, random numbers are inserted in the idle state to ensure transmission , Therefore, the random data other than the received valid signal assertion need not be paid too much attention .

Create a flow mode project

In the configuration Aurora IP when , Interface mode selection stream Flow mode .

Then repeat the steps that just generated the routine .

Stream mode code structure

The code structure of stream mode is similar to that of frame mode , Because it is a stream mode , Compared with the frame mode, the signals at the sending and receiving ends are a few less , For example, the following ports are missing from the data generation module ：TX_SOF_N,TX_EOF_N,TX_REM, And the signal here , After conversion LL The interface is converted to AXI After the interface , The signal will decrease accordingly .

Compared with the frame mode, the main body of the module code at the sending end of the stream mode has less complex state machine design , Only the pseudo-random number generation part is left . Receiving also reduces the decoding of frame data .

View simulation

The simulation results are similar to the transmission in frame mode , The transmission result is correct .

reference

1. PG046
2. Aurora IP routine
3. FPGA Design experience （6）Aurora IP Nuclear example analysis and simulation （framing edition ）