Icc2 analysis timing artifact analyze_ design_ violations

How to analyze and solve timing violations is a big mountain in front of novices , And frequency reduction , use LVT, Support area , It is the three board mountain axe , Of course, not all clappers are so talkative , Therefore, learning to analyze and solve timing violations has become a necessary skill for back-end engineers to travel at home （ Waving a three board axe also makes you famous ）.

ICC2 Provide analyze_design_violations The order of , Assist users to analyze timing violations , It avoids the painful process of analyzing a large number of sequence violations one by one .

analyze_timing_violations Support setup、hold analysis ,transition、noise,only_lib Analysis of . Here we use hold violation As an example ：

icc2_shell> analyze_timing_vilations -type hold

Have a look first ,hold violation There are those reasons , What are the corresponding numbers .

According to the report, we can see ,519 strip “Small violations”, This kind of small is too lazy to analyze at ordinary times path Put it aside , Focus on the causes of other problems ：

H1：Large clock skew（LCS） Two article , Use the graphical interface to expand clock tree analysis , Output definition generate clock Of reg To the same clock domain sink Between hold violation,setup There is not enough margin , The two roads ahead , Or adjust tree, Try to put tree Make short , Or analyze data path, Harden your scalp and repair . Here is a cold knowledge ,delay cell In different pvt corner The delay offset under is relatively large , If you find that path There is a pile of delay cell,hold violation It hasn't been repaired ,setup The margin is not enough , You can try delay cell Switch to buffer, Then insert buffer Go and fix it .

Here you can go through report_clock_timing -type skew -from xx/CK -to xx/CK To report launch clock And capture clock Between local skew, Compare with report_clock_qor,report_clock_timing The report local skew It's about thinking about derate Of , It's in line with report_timing What you see clock network delay.

except skew Caused by the violation problem , There is another item in the report H9：Remaining violation （OT）, This part belongs to unclassified timing violation, But don't worry , The tool also provides net analysis , Here's the picture , although path There is no classification in the analysis , But as long as there is violation, Tools always give a reason .

Continue analysis timing violation, Find unclassified in the report （OT） Of violation path.

although path The analysis does not give violation reason , however net When analyzing, I told this path There is one on the net After high density area（DEN）, Select this in the graphical interface net, Here's the picture , Come to the conclusion , Excessive local utilization leads to hold insert buffer No place to find .

At this point, the time series analysis is over , It should be adjusted later tree transfer tree, It's time to plug in buffer insert buffer, It can't be solved, and the frequency can be reduced , in VT, Support area .