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Implementation of VGA protocol based on FPGA
2022-06-11 16:04:00 【Protect the milk cat】
List of articles
One 、VGA brief introduction
VGA(Video Graphics Array) yes IBM stay 1987 Annual follow PS/2 machine ⼀ From the launch of ⼀ Kinds of video , With resolution ⾼、 display ⽰ Fast speed 、 Yan ⾊ Rich and other advantages , In color ⾊ display ⽰ The device field has been ⼴ Universal response ⽤. No ⽀ Hold hot plug , No ⽀ a ⾳ Frequency transmission . about ⼀ Some inlays ⼊ type VGA display ⽰ System , It can be done without ⽤VGA display ⽰ Cards and computers Under the circumstances , Realization VGA The display of the image ⽰ And control .VGA display ⽰ The utility model has the advantages of low cost 、 Simple structure 、 Should be ⽤ The advantages of flexibility .
Display principle
VGA Analog voltage through the pin (0V-0.714V) Show red, green and blue , Different voltage values correspond to different colors .
VGA The monitor is driven by scanning , Generally, it is progressive scanning .
Progressive scanning is scanning from the top left corner of the screen , Scan from left to right , Every line scanned , The beam returns to the beginning of the next line on the left side of the screen , in the meantime ,CRT Blanking the electron beam , At the end of each line , Use the line synchronization signal to synchronize ;
When all the lines are scanned , After forming a frame , Field synchronization with field synchronization signal , And bring the scan back to the top left of the screen , At the same time, field blanking is carried out , Start the next frame .
FPGA Chip driver VGA Show , Analog signals need to be generated first , This requires the help of a digital to analog converter D/A, utilize D/A Generate analog signals , Output to VGA Of RED、GREEN、BLUE Primary color data line .
Two 、 Show characters
Font software ：
https://pan.baidu.com/s/1LLpNgYiH5zf6sXZoU8j9aw
Extraction code ：8888
Implementation code ：
module VGA_display(
OSC_50, // primary CLK2_50 Clock signal
VGA_CLK, //VGA Self clock
VGA_HS, // Line sync
VGA_VS, // Field synchronization signal
VGA_BLANK, // Composite blank signal control signal When BLANK It is the blanking level of analog video output at low level , At that moment, from R9~R0,G9~G0,B9~B0 All data entered is ignored
VGA_SYNC, // In accordance with the synchronization control signal Both line timing and field timing should generate synchronization pulses
VGA_R, //VGA green
VGA_B, //VGA Blue
VGA_G); //VGA green
input OSC_50; // External clock signal CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; // The leading edge signal period of line synchronization is long
parameter H_SYNC = 96; // The period of line synchronization signal is long
parameter H_BACK = 48; // The signal period of the trailing edge of line synchronization is long
parameter H_ACT = 640; // The line display cycle is long
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; // The total period of line blank signal is long
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; // The total line cycle is long and time-consuming
parameter V_FRONT = 11; // The signal period at the front of field synchronization is long
parameter V_SYNC = 2; // The period of field synchronization signal is long
parameter V_BACK = 31; // The signal period at the trailing edge of field synchronization is long
parameter V_ACT = 480; // Long field display period
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; // The total period of field blank signal is long
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; // The total period of the field is long and time-consuming
reg [10:0] H_Cont; // Line cycle counter
reg [10:0] V_Cont; // Field period counter
wire [7:0] VGA_R; //VGA Red control line
wire [7:0] VGA_G; //VGA Green control line
wire [7:0] VGA_B; //VGA Blue control line
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; // The number of pixels in the current line
reg [10:0] Y; // Which line of the current field
reg CLK_25;
[email protected](posedge OSC_50)
begin
CLK_25=~CLK_25; // The clock
end
assign VGA_SYNC = 1'b0; // Synchronization signal low level
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); // When the row counter is less than the total length of the row blank or the field counter is less than the total length of the field blank , Blank signal low level
assign VGA_CLK = ~CLK_to_DAC; //VGA The clock is equal to CLK_25 Take the opposite
assign CLK_to_DAC = CLK_25;
[email protected](posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) // If the row counter is less than the total row time
H_Cont<=H_Cont+1'b1; // Row counter +1
else H_Cont<=0; // Otherwise, the line counter is cleared
if(H_Cont==H_FRONT-1) // If the row counter is equal to the blank time at the leading edge of the row -1
VGA_HS<=1'b0; // The line synchronization signal is set to 0
if(H_Cont==H_FRONT+H_SYNC-1) // If the row counter is equal to the row leading edge + Line synchronization -1
VGA_HS<=1'b1; // The line synchronization signal is set to 1
if(H_Cont>=H_BLANK) // If the row counter is greater than or equal to the total length of row blank
X<=H_Cont-H_BLANK; //X Equal to the row counter - Total length of blank lines （X Is the number of pixels in the current line ）
else X<=0; // otherwise X by 0
end
[email protected](posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) // If the field counter is less than the total row time
V_Cont<=V_Cont+1'b1; // Field counter +1
else V_Cont<=0; // Otherwise, the field counter is cleared
if(V_Cont==V_FRONT-1) // If the field counter is equal to the field leading edge blank time -1
VGA_VS<=1'b0; // The field synchronization signal is set to 0
if(V_Cont==V_FRONT+V_SYNC-1) // If the field counter is equal to the leading edge of the row + Field synchronization -1
VGA_VS<=1'b1; // The field synchronization signal is set to 1
if(V_Cont>=V_BLANK) // If the field counter is greater than or equal to the total time of field blank
Y<=V_Cont-V_BLANK; //Y Equal to the field counter - Total duration of field blank （Y For the line number of the current field ）
else Y<=0; // otherwise Y by 0
end
reg valid_yr;
[email protected](posedge CLK_to_DAC)
if(V_Cont == 10'd32) // Field counter =32 when
valid_yr<=1'b1; // Line input activates
else if(V_Cont==10'd512) // Field counter =512 when
valid_yr<=1'b0; // Line input freeze
wire valid_y=valid_yr; // attachment
reg valid_r;
[email protected](posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) // Row counter =32 when
valid_r<=1'b1; // Pixel input active
else if((H_Cont==10'd512)&&valid_y) // Row counter =512 when
valid_r<=1'b0; // Pixel input is frozen
wire valid = valid_r; // attachment
wire[10:0] x_dis; // Pixel display control signal
wire[10:0] y_dis; // The line shows the control signal
assign x_dis=X; // attachment X
assign y_dis=Y; // attachment Y
parameter // Dot matrix font ： Every line char_lineXX Is a line displayed , common 272 Column
char_line00=272'h000000000000000000000000000000000000, // The first 1 That's ok
char_line01=272'h020001000028000000000000000000000000, // The first 2 That's ok
char_line02=272'h0400FFFE4024000000000000000000000000, // The first 3 That's ok
char_line03=272'h080001002020000000000000000000000000, // The first 4 That's ok
char_line04=272'h7FFC3FF827FE183C0838187E1818183C3C7E, // The first 5 That's ok
char_line05=272'h400400000420244238442442242424424240, // The first 6 That's ok
char_line06=272'h40041FF00420404208424204424042424240, // The first 7 That's ok
char_line07=272'h47C41010E424400208424204424042024240, // The first 8 That's ok
char_line08=272'h44441FF027A45C0408424208425C42040278, // The first 9 That's ok
char_line09=272'h4444082024A4621808464208426242180444, // The first 10 That's ok
char_line0a=272'h4444FFFE24A84204083A4210424242040802, // The first 11 That's ok
char_line0b=272'h4444100024A8420208024210424242021002, // The first 12 That's ok
char_line0c=272'h47C47F7C2C90424208024210424242422042, // The first 13 That's ok
char_line0d=272'h444411443692224208242410242224424244, // The first 14 That's ok
char_line0e=272'h40042144292A1C3C3E181810181C183C7E38, // The first 15 That's ok
char_line0f=272'h4014457C0846000000000000000000000000, // The first 16 That's ok
char_line10=272'h400882441082000000000000000000000000, // The first 17 That's ok
char_line11=272'h000000000000000000000000000000000000, // The first 18 That's ok
char_line12=272'h000000000000000000000000000000000000, // The first 19 That's ok
char_line13=272'h000000000000000000000000000000000000, // The first 20 That's ok
char_line14=272'h000000000000000000000000000000000000, // The first 21 That's ok
char_line15=272'h000000000000000000000000000000000000, // The first 22 That's ok
char_line16=272'h000000000000000000000000000000000000, // The first 23 That's ok
char_line17=272'h000000000000000000000000000000000000, // The first 24 That's ok
char_line18=272'h000000000000000000000000000000000000, // The first 25 That's ok
char_line19=272'h000000000000000000000000000000000000, // The first 26 That's ok
char_line1a=272'h000000000000000000000000000000000000, // The first 27 That's ok
char_line1b=272'h000000000000000000000000000000000000, // The first 28 That's ok
char_line1c=272'h000000000000000000000000000000000000, // The first 29 That's ok
char_line1d=272'h000000000000000000000000000000000000, // The first 30 That's ok
char_line1e=272'h000000000000000000000000000000000000, // The first 31 That's ok
char_line1f=272'h000000000000000000000000000000000000; // The first 32 That's ok
reg[8:0] char_bit;
[email protected](posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd272; // When displayed to 144 Pixel ready to start outputting image data
else if(X>10'd144&&X<10'd416) // Left margin screen 144 Pixels to 416 When the pixel 416=144+272（ The width of the image ）
char_bit<=char_bit-1'b1; // Output image information upside down
reg[29:0] vga_rgb; // Define color cache
[email protected](posedge CLK_to_DAC)
if(X>10'd144&&X<10'd416) //X Controls the horizontal display boundary of the image ： Left margin to the left of the screen 144 Pixels The right boundary is away from the left boundary of the screen 416 Pixels
begin case(Y) //Y Controls the vertical display boundary of the image ： From the top of the screen 160 Pixels begin to display the first row of data
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; // If the row has data The color is red
else vga_rgb<=30'b0000000000_0000000000_0000000000; // Otherwise black
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; // Default color black
endcase
end
else vga_rgb<=30'h000000000; // Otherwise black
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
result ：
3、 ... and 、 Show colored stripes
Top level modules
module vga_colorbar( 2 input sys_clk, // The system clock
input sys_rst_n, // Reset signal
//VGA Interface
output vga_hs, // Line sync
output vga_vs, // Field synchronization signal
output [15:0] vga_rgb // Red, green and blue primary color output
);
//wire define
wire vga_clk_w; //PLL Divide the frequency to get 25Mhz The clock
wire locked_w; //PLL Output stable signal
wire rst_n_w; // Internal reset signal
wire [15:0] pixel_data_w; // Pixel data
wire [ 9:0] pixel_xpos_w; // Abscissa of pixel
wire [ 9:0] pixel_ypos_w; // Pixel ordinate
//*****************************************************
//** main code
//*****************************************************
// stay PLL After the output is stable , Stop reset
assign rst_n_w = sys_rst_n && locked_w;
vga_pll u_vga_pll( // Clock division module
.inclk0 (sys_clk),
.areset (~sys_rst_n),
.c0 (vga_clk_w), //VGA The clock 25M
.locked (locked_w)
);
vga_driver u_vga_
.vga_clk (vga_clk_w),
.sys_rst_n (rst_n_w),
.vga_hs (vga_hs),
.vga_vs (vga_vs),
.vga_rgb (vga_rgb),
.pixel_data (pixel_data_w),
.pixel_xpos (pixel_xpos_w),
.pixel_ypos (pixel_ypos_w)
);
vga_display u_vga_display(
.vga_clk (vga_clk_w),
.sys_rst_n (rst_n_w),
.pixel_xpos (pixel_xpos_w),
.pixel_ypos (pixel_ypos_w),
.pixel_data (pixel_data_w)
);
endmodule
Driver module
module vga_driver( 2 input vga_clk, //VGA Drive clock
input sys_rst_n, // Reset signal
//VGA Interface
output vga_hs, // Line sync
output vga_vs, // Field synchronization signal
output [15:0] vga_rgb, // Red, green and blue primary color output
input [15:0] pixel_data, // Pixel data
output [ 9:0] pixel_xpos, // Abscissa of pixel
output [ 9:0] pixel_ypos // Pixel ordinate
);
//parameter define
parameter H_SYNC = 10'd96; // Line synchronization
parameter H_BACK = 10'd48; // The line shows the trailing edge
parameter H_DISP = 10'd640; // Row valid data
parameter H_FRONT = 10'd16; // The row shows the leading edge
parameter H_TOTAL = 10'd800; // Line scan cycle
parameter V_SYNC = 10'd2; // Field synchronization
parameter V_BACK = 10'd33; // The field displays the trailing edge
parameter V_DISP = 10'd480; // Field valid data
parameter V_FRONT = 10'd10; // The field shows the leading edge
parameter V_TOTAL = 10'd525; // Field scanning period
//reg define
reg [9:0] cnt_h;
reg [9:0] cnt_v;
//wire define
wire vga_en;
wire data_req;
//** main code
//VGA Field synchronization signal
assign vga_hs = (cnt_h <= H_SYNC - 1'b1) ? 1'b0 : 1'b1;
assign vga_vs = (cnt_v <= V_SYNC - 1'b1) ? 1'b0 : 1'b1;
// RGB565 Data output enable signal
assign vga_en = (((cnt_h >= H_SYNC+H_BACK) && (cnt_h < H_SYNC+H_BACK+H_DISP))
&&((cnt_v >= V_SYNC+V_BACK) && (cnt_v < V_SYNC+V_BACK+V_DISP)))
? 1'b1 : 1'b0;
//RGB565 Data output
assign vga_rgb = vga_en ? pixel_data : 16'd0;
// Pixel color data input request signal
assign data_req = (((cnt_h >= H_SYNC+H_BACK-1'b1) && (cnt_h < H_SYNC+H_BACK+H_DISP-1'b1))
&& ((cnt_v >= V_SYNC+V_BACK) && (cnt_v < V_SYNC+V_BACK+V_DISP)))
? 1'b1 : 1'b0;
// Pixel coordinates
assign pixel_xpos = data_req ? (cnt_h - (H_SYNC + H_BACK - 1'b1)) : 10'd0;
assign pixel_ypos = data_req ? (cnt_v - (V_SYNC + V_BACK - 1'b1)) : 10'd0;
// The row counter counts the pixel clock
always @(posedge vga_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
cnt_h <= 10'd0;
else begin
if(cnt_h < H_TOTAL - 1'b1)
cnt_h <= cnt_h + 1'b1;
else
cnt_h <= 10'd0;
end
end
// Field counter counts rows
always @(posedge vga_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
cnt_v <= 10'd0;
else if(cnt_h == H_TOTAL - 1'b1) begin
if(cnt_v < V_TOTAL - 1'b1)
cnt_v <= cnt_v + 1'b1;
else
cnt_v <= 10'd0;
end
end
endmodule
Display module
module vga_display( 2 input vga_clk, //VGA Drive clock
input sys_rst_n, // Reset signal
input [ 9:0] pixel_xpos, // Abscissa of pixel
input [ 9:0] pixel_ypos, // Pixel ordinate
output reg [15:0] pixel_data // Pixel data
);
parameter H_DISP = 10'd640; // The resolution of the — That's ok
parameter V_DISP = 10'd480; // The resolution of the — Column
localparam WHITE = 16'b11111_111111_11111; //RGB565 white
localparam BLACK = 16'b00000_000000_00000; //RGB565 black
localparam RED = 16'b11111_000000_00000; //RGB565 Red
localparam GREEN = 16'b00000_111111_00000; //RGB565 green
localparam BLUE = 16'b00000_000000_11111; //RGB565 Blue
//*****************************************************
//** main code
//*****************************************************
// Specifies the current pixel color data according to the current pixel coordinates , Display color bars on the screen
always @(posedge vga_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
pixel_data <= 16'd0;
else begin
if((pixel_xpos >= 0) && (pixel_xpos < (H_DISP/5)*1))
pixel_data <= WHITE;
else if((pixel_xpos >= (H_DISP/5)*1) && (pixel_xpos < (H_DISP/5)*2))
pixel_data <= BLACK;
else if((pixel_xpos >= (H_DISP/5)*2) && (pixel_xpos < (H_DISP/5)*3))
pixel_data <= RED;
else if((pixel_xpos >= (H_DISP/5)*3) && (pixel_xpos < (H_DISP/5)*4))
pixel_data <= GREEN;
else
pixel_data <= BLUE;
end
end
endmodule
result ：
Four 、 reference
be based on Verilog Programming to realize VGA Image display for
【FPGA experiment 】 be based on DE2-115 Platform VGA Show
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