Using SystemVerilog to describe a state machine

Use Systemverilog Description state machine

The state of the system must be stored in internal registers . stay SystemVerilog In language , States can be enumerated (enumerated type) Express . Possible values of this type are state names , Variables are listed after a list of possible values . for example :

enum{s0,s1,..} state;

In the following code , There are two process blocks . Each process block is marked with its own name . The first one is marked with SEO The process block of describes a state machine . The process block waits for the arrival of the positive jump edge of the clock , Or wait for the arrival of the negative jump edge of the reset signal . The first test is the asynchronous reset signal , If the negative jump edge of the reset signal arrives , The default value is G Assigned to the state variable state. otherwise , Jump to case Statement branch , Enter different branches according to the current status value . therefore ,case Each branch of a statement is equivalent to a graph 6.9 One of the two states in and the judgment box . In the first branch , Test if a car is coming (car It's true / false ), Then set the State . If no car comes (car=0), The state remains unchanged ( That is still G). Declare the procedure block as always_ff block , It is therefore expected that this state will be mapped to one or more triggers triggered by a positive jump edge . Other states are constructed in a similar way .

The second one is marked with OP In the process block of , The output is set to 1. The process block is a corresponding to combinatorial logic always_comb block . Note that at the beginning of the process block, it is start_timer And other outputs 0. This example is a good practice , Because this writing can ensure that the latch will not be generated due to the negligence of code writing . Use again in the process block case sentence , This structure is related to ASM Figure corresponds to . In each state , Assign a value to the unconditional output ; The conditional assignment follows if After conditional statement .

module traffic_1 (
	output logic start_timer,major_green,mintor_green,
	input logic clock,n_reset,timed,car