ROM of IP core

ROM summary

        ROM Read only memory （Read-Only Memory） For short , It is a solid-state semiconductor memory that can only read out the data stored in advance . Its characteristic is that once the data is stored, it can no longer be changed or deleted , And the data will not disappear because the power is turned off .

And in fact FPGA Pass through IP Nucleated ROM or RAM All the calls are FPGA Inside RAM resources , Power down content will be lost （ It's also easy to explain ,FPGA There is no power down nonvolatile memory unit inside the chip ）. use IP Nucleated ROM The module just adds data files in advance （.mif or .hex Format ）, stay FPGA At run time, data files are sent to ROM Module initialization , So that ROM The module is like a “ real ” Power down nonvolatile memory ; That's why ,ROM The contents of the module must be written in the data file in advance , Cannot modify... In a circuit .

       Altera To launch the ROM IP There are two types of nuclei ： Single port ROM And dual port ROM.

Single port ROM ： Provide a read address port and a read data port , Read only ;

Dual port ROM：  With single port ROM similar , The difference is that it provides two read address ports and two read data ports , Basically, it can be regarded as two single ports RAM Splicing into .

                                                  Single port ROM Interface signal

Dual port ROM Interface signal

Single port ROM Configuration of

Let's create a new project under the project directory ip_core Folder , take IP The underwriting is stored in this folder and named rom_256x8（rom We call IP nucleus ,256 It's called IP Nuclear capacity ,8 It's called IP Nuclear data bit width . The name here is for the convenience of identifying what we created IP Nuclear type and resources , The data file we make has a capacity of 256, The data bit width is 8bit）.

        Select the clock mode to use , You can choose single clock or double clock . When selecting a single clock, use one clock to control all registers of the storage block , When double clock is selected, input clock control address register , Output clock control data output register .ROM Mode is not write enabled 、 Byte enable and data input registers . Here we choose the default option Single clock（ Single clock ）.

The figure above shows whether to output “q” register . Here we remove the register of the output port （ If not removed word , It will delay the output by one beat . If there is no special demand, we don't need to delay this shot ）.

When not checked , The data output will delay the address input by one clock cycle , When checked , The clock signal will input a higher frequency , The data output will delay the address input for two clock cycles

The above figure shows adding a file path  

It reminds us that we need to add a third-party simulation tool named “altera_mf” The library of

Dual port ROM Configuration of

As a number of words” It is determined by the number of words ,“AS a number of bits” It is determined by the number of bits .

（ Be careful ： The selected capacity should be greater than the data volume of the data file we need to write

 Single clock（ Single clock ）： Use a clock to control .

Dual clock：use separate “input” and “output”clocks（ Dual clock ： Use separate input clock and output clock ）： The input and output clocks control the relevant registers of the data input and output of the storage block respectively .

Dual clock：use separate clocks for A and B ports（ Dual clock ： port A And port B Use different independent clocks ）： The clock A Control port A All the registers of , The clock B Control port B All the registers of .

ROM IP The use of the core

The goal of the experiment

take ROM The data in is read out and displayed on the nixie tube . We ROM The initialization data for is 0~255, That is to save data

0~255. Then every 0.2s We from 0 The address starts to read down, and the data is displayed on the nixie tube , We use two key signals to read the data of the specified address , Every time you press a key, the data of an address is read and displayed on the nixie tube . Press the key again , Continue at the current address with 0.2s Read the data down and display it .

 ROM IP Nuclear modules

 ROM Control module

from ROM According to our data book , The read operation is triggered on the rising edge of the clock , And we're calling ROM There is no generated read enable , So in Read the rising edge of the clock. As long as we give the corresponding address, we can read the data in the address on the rising edge of the clock . In this module, we only need to control the generation of read addresses .

  ROM Control module input and output signals      

      ROM Not only from 0 Address start reading , It can read any address specified , To verify this function , We add two key signals , Press each key to read out the data of a specified address , Press again to read along the current address sequence .

      addr_flag1 、 addr_flag2 ： read The earth site Of mark Records Letter Number . When Press Next Press key 1/ Press key 2

（key1_flag/key2_flag=1） when , Let the flag signal of the read address be high , Press again to make the flag signal of reading address low , We can use a negate operation to complete . When you press the key 1 Press after ,addr_flag1 Read address for high 99 The data of ; When you press the button 2 after ,addr_flag2 Read address for high 199 The data of （ You can get the address at will , As long as ROM The address range of ）. What needs to be noted here is Because we can only read the signal of one address at a time , So when we pull up one address flag signal, we should set the other address flag signal to 0, In this way, the read address will not conflict .

ROM Control module reference code (rom_ctrl.v)

module  rom_ctrl
#(
   parameter  CNT_MAX = 24'd9_999_999
)
(
   input  wire          sys_clk  ,
   input  wire          sys_rst_n,
   input  wire          key1     ,     // Key 1 Effective signal after chattering elimination 
   input  wire          key2     ,     // Key 2 Effective signal after chattering elimination 
   
   output reg   [7:0]  addr            // Output read ROM Address 
);

reg   [23:0]  cnt_200ms ;
reg           key1_en;                 // Specific address  1  Sign signal 
reg           key2_en;                 // Specific address  2  Sign signal 

//0.2s  Cycle count 
[email protected](posedge sys_clk or negedge sys_rst_n)
   if(sys_rst_n == 1'b0)
       cnt_200ms <= 24'd0;
   else  if(cnt_200ms == CNT_MAX || key1_en == 1'b1 || key2_en == 1'b1)
       cnt_200ms <= 24'd0;
   else 
       cnt_200ms <= cnt_200ms + 1'b1;

// Generate a specific address  1  Sign signal 
[email protected](posedge sys_clk or negedge sys_rst_n)
   if(sys_rst_n == 1'b0)
       key1_en <= 1'b0;
   else  if(key2 == 1'b1)
       key1_en <= 1'b0;
   else if(key1 == 1'b1)
       key1_en <= ~key1_en;
   else
       key1_en <= key1_en;
	   
/ Generate a specific address  2  Sign signal 
[email protected](posedge sys_clk or negedge sys_rst_n)
   if(sys_rst_n == 1'b0)
       key2_en <= 1'b0;
   else  if(key1 == 1'b1)
       key2_en <= 1'b0;
   else if(key2 == 1'b1)
       key2_en <= ~key2_en;
   else
       key2_en <= key2_en;

// Let the address change from  0~255  loop , Two of the keys control the jump of two specific addresses 
[email protected](posedge sys_clk or negedge sys_rst_n)
   if(sys_rst_n == 1'b0)
       addr <= 8'd0;
   else if(addr == 8'd255 && cnt_200ms == CNT_MAX)
       addr <= 8'd0;
   else if(key1_en == 1'b1)
       addr <= 8'd99;
   else if(key2_en == 1'b1)
       addr <=8'd199;
   else if(cnt_200ms == CNT_MAX)
       addr <= addr + 1'b1;

endmodule

Top level modules

rom The top-level module is mainly the instantiation of each sub function module , And the connection of the corresponding signal

 

rom The top-level module is mainly the instantiation of each sub function module , And the connection of the corresponding signal , Coding is easier , There is no need to draw the waveform

module rom
(
   input  wire    sys_clk,
   input  wire    sys_rst_n,
   input  wire    key1     ,
   input  wire    key2     ,
   
   output wire    ds,
   output wire    oe,
   output wire    shcp,
   output wire    stcp
);

wire           key1_flag;  // Key  1  Dithering signal 
wire           key2_flag;  // Key  2  Dithering signal 
wire  [7:0]    addr;
wire  [7:0]    data;       // read out  ROM  data 

key_filter
#(
    .CNT_MAX (20'd999_999)
)
key_filter_inst1
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .key_in   (key1),
   
   .key_flag (key1_flag)     //key_flag  by  1  When, it means that the key is pressed after shaking elimination 
);

key_filter
#(
    .CNT_MAX (20'd999_999)
)
key_filter_inst2
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .key_in   (key2),
   
   .key_flag (key2_flag)     //key_flag  by  1  When, it means that the key is pressed after shaking elimination 
);

rom_ctrl
#(
   .CNT_MAX (24'd9_999_999)
)
rom_ctrl_inst
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .key1     (key1_flag),      // Key  1  Effective signal after chattering elimination  
   .key2     (key2_flag),      // Key  2  Effective signal after chattering elimination 
   
   .addr     (addr)            // Output read  ROM  Address 
);

rom_8x256	rom_8x256_inst 
(
	.address ( addr ),
	.clock ( sys_clk ),
	.q ( data )
	);
	
seg_595_dynamic seg_595_dynamic
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .data     ({12'b0,data}),
   .point    (6'b000_000),      // Decimal point display , High active 
   .sign     (1'b0),            // Sign bit , The high level displays a negative sign 
   .seg_en   (1'b1),            // Nixie tube enable signal , High active 
  
   .ds       (ds  ),       // Serial data input 
   .oe       (oe  ),       // Output enable signal 
   .shcp     (shcp),       // Clock input of shift register 
   .stcp     (stcp)        // The output data is stored and sent to the clock 
);

endmodule

 RTL View      

 ROM IP Nuclear simulation

`timescale 1ns/1ns
module tb_rom();

reg   sys_clk;
reg   sys_rst_n;
reg   key1;
reg   key2;

wire  ds;
wire  oe;
wire  shcp;
wire  stcp;

initial
     begin
	    sys_clk = 1'b1;
		sys_rst_n   <= 1'b0;
		key1  <= 1'b1;
		key2  <= 1'b1;
		#20
		sys_rst_n   <= 1'b1;
		#700000                   // The simulation is 100 Clock cycles , One clock cycle 20ns, That's one 
                                  // The display time of the data is 100*20=2000ns,
                           //256 Data display time is 256*2000=512000ns, Therefore, the delay time needs to be greater than this value 

//key1
		key1  <= 1'b0;
		#20
		key1  <= 1'b1;
		#20
		key1  <= 1'b0;
		#20
		key1  <= 1'b1;
		#20
		key1  <= 1'b0;
		#200                           // The above is to simulate the jitter before pressing the key , The following is a simulation of the jitter after pressing a key 
		key1  <= 1'b1;
		#20
		key1  <= 1'b0;
		#20
		key1  <= 1'b1;
		#20
		key1  <= 1'b0;
		#20
		key1  <= 1'b1;
//key2
        #20000
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#200                          // The above is to simulate the jitter before pressing the key , The following is a simulation of the jitter after pressing a key 
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
//key2
        #20000
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#200                         // The above is to simulate the jitter before pressing the key , The following is a simulation of the jitter after pressing a key 
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
		#20
		key2  <= 1'b0;
		#20
		key2  <= 1'b1;
	 end
	 
always #10 sys_clk = ~sys_clk;
//defparam   rom_inst.key_filter_indt1.CNT_MAX = 9;

rom  rom_inst
(
   .sys_clk  (sys_clk  ),
   .sys_rst_n(sys_rst_n),
   .key1     (key1     ),
   .key2     (key2     ),
  
   .ds       (ds       ),
   .oe       (oe       ),
   .shcp     (shcp     ),
   .stcp     (stcp     )
);

endmodule

Next, the simulation verifies