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set_ multicycle_ path

2022-07-28 06:34:00 【Shilu building】

set_multicycle_path Shorthand of common scenes and commands ：

1、 Same clock or same cycle synchronization clock

set_multicycle_path N -setup -from CLK1 -to CLK2
set_multicycle_path N-1 -hold -from CLK1 -to CLK2

2、 Synchronous frequency division clock , Fast, slow

set_multicycle_path N -setup -start -from CLK1 -to CLK2
set_multicycle_path N-1 -hold （-start）-from CLK1 -to CLK2

3、 Synchronous frequency division clock , Slow and fast

set_multicycle_path N -setup （-end）-from CLK1 -to CLK2
set_multicycle_path N-1 -hold -end -from CLK1 -to CLK2

In waveform analysis ,-start Move default launch edge（setup towards the left ,hold towards the right ）,-end Move default capture edge（setup towards the right ,hold towards the left ）.

1 The same clock or synchronous clock of the same cycle

stay STA Some in the analysis data path When the length exceeds one clock cycle , We can aim at this path Use multicycle path, Change the number of cycles to capture data .

The following example ,setup check They found UFF0/Q To UFF1/D Of data path The length is about three clock cycles （ Pictured 1）, Set up multicycle path Collect data once every clock cycle （Default capture） Instead, collect data every three cycles （New capture edge）.

create_clock - name CLKM - period 10 [ get_ports CLKM]
set_multicycle_path 3 - setup - from [ get_pins UFF0/Q] - to [ get_pins UFF1/D]

chart 1

Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLKM)
Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLKM)
Path Group: CLKM
Path Type: max
SCENARIO：FUNC_SLOW_CMAX-40
Point                                     Incr         Path
---------------------------------------------------------------
clock CLKM (rise edge)                    0.00         0.00
clock network delay (propagated)          0.11         0.11
UFF0/CK (DFF )                            0.00         0.11 r
UFF0/Q (DFF ) <-                          0.14         0.26 f
UNOR0/ZN (NR2 )                           0.04         0.30 r
UBUF4/Z (BUFF )                           0.05         0.35 r
... (...)                                28.00        28.00 
UFF1/D (DFF )                             0.00        28.35 r
data arrival time                                     28.35
clock CLKM (rise edge)                   30.00         30.00
clock network delay (propagated)          0.12         30.12
clock uncertainty                        -0.30         29.82
UFF1/CK (DFF )                                         29.82 r
library setup time                       -0.04         29.78
data required time                                     29.78
---------------------------------------------------------------
data required time                                     29.78
data arrival time                                     -28.35
---------------------------------------------------------------
slack (MET)                                             1.43

here hold check Along the default in setup capture edge The previous significant edge of （ Here is the rising edge trigger ）, But this way hold check Can not met, So you need to give hold check Set up a set_multicycle_path. Give Way UFF1/CK Of hold check Two cycles in advance （ Pictured 2）.

set_multicycle_path 2 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

chart 2

Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLKM)
Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLKM)
Path Group: CLKM
Path Type: min
SCENARIO：FUNC_FAST_CMIN125
Point                                        Incr      Path
---------------------------------------------------------------
clock CLKM (rise edge)                       0.00      0.00
clock source latency                         0.00      0.00
CLKM (in)                                    0.00      0.00 r
UCKBUF0/C (CKB )                             0.03      0.03 r
UCKBUF1/C (CKB )                             0.03      0.06 r
UFF0/CK (DFF )                               0.00      0.06 r
UFF0/Q (DFF ) <-                             0.07      0.13 r
UNOR0/ZN (NR2 )                              0.01      0.14 f
UBUF4/Z (BUFF )                              0.03      0.17 f
... (...)                                   14.00     14.00
UFF1/D (DFF )                                0.00     14.17 f
data arrival time                                     14.17
clock CLKM (rise edge)                       0.00      0.00
clock source latency                         0.00      0.00
CLKM (in)                                    0.00      0.00 r
UCKBUF0/C (CKB )                             0.03      0.03 r
UCKBUF2/C (CKB )                             0.03      0.06 r
UFF1/CK (DFF )                               0.00      0.06 r
clock uncertainty                            0.02      0.08
library hold time                            0.01      0.09
data required time                                     0.09
---------------------------------------------------------------
data required time                                     0.09
data arrival time                                    -14.17
---------------------------------------------------------------
slack (VIOLATED)                                      14.08

In conclusion , Most designs allow setup check Delay to N Collect data in cycles , Then we need to let hold check advance N-1 A cycle , Go back to and launch edge Check along .（ Normal synchronization clock setup check N=1, namely capture edge stay launch edge The effective edge of the next clock cycle ,N-1=0, namely hold check And launch edge Check along .）

Or the example above , If you just let setup check Delay two cycles （N=3）, Not allow hold check advance （N-1=2） How about two cycles ？（ Pictured 3）hold check stay setup check capture edge The previous rising edge of .hold check unable met.

chart 3

Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLKM)
Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLKM)
Path Group: CLKM
Path Type: min
SCENARIO：FUNC_FAST_CMIN125
Point                                        Incr      Path
---------------------------------------------------------------
clock CLKM (rise edge)                       0.00      0.00
clock source latency                         0.00      0.00
CLKM (in)                                    0.00      0.00 r
UCKBUF0/C (CKB )                             0.03      0.03 r
UCKBUF1/C (CKB )                             0.03      0.06 r
UFF0/CK (DFF )                               0.00      0.06 r
UFF0/Q (DFF ) <-                             0.07      0.13 r
UNOR0/ZN (NR2 )                              0.01      0.14 f
UBUF4/Z (BUFF )                              0.03      0.17 f
... (...)                                   14.00     14.00
UFF1/D (DFF )                                0.00     14.17 f
data arrival time                                     14.17
clock CLKM (rise edge)                       0.00     20.00
clock source latency                         0.00     20.00
CLKM (in)                                    0.00     20.00 r
UCKBUF0/C (CKB )                             0.03     20.03 r
UCKBUF2/C (CKB )                             0.03     20.06 r
UFF1/CK (DFF )                               0.00     20.06 r
clock uncertainty                            0.02     20.08
library hold time                            0.01     20.09
data required time                                    20.09
---------------------------------------------------------------
data required time                                    20.09
data arrival time                                    -14.17
---------------------------------------------------------------
slack (VIOLATED)                                      -5.92

2 Slow and fast

data path From low-speed clock to high-speed clock ,clock Define the following example , default launch And capture edge Pictured 5 .

create_clock -name CLKM \
-period 20 -waveform {0 10} [get_ports CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]

chart 5

hypothesis data path More than three in length CLKP The cycle of , here setup check Excess and tension , Set up muticycle path Give Way capture edge Three cycles ahead . Pictured 6 .

set_multicycle_path 4 -setup \
-from [get_clocks CLKM] -to [get_clocks CLKP] -end

chart 6

here hold check Excess and tension , Need to put hold check Return to launch edge Location . Pictured 7.

set_multicycle_path 3 -hold \
-from [get_clocks CLKM] -to [get_clocks CLKP] -end

chart 7

3 Fast, slow

data path From tell clock to low-speed clock ,clock Examples of definitions are as follows , default setup、hold check Pictured 8 .

create_clock -name CLKM \
-period 20 -waveform {0 10} [get_ports CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]

chart 8

setup check There are four situations ,setup1、setup2、setup3 and setup4, The most urgent one is setup4, Corresponding setup check Four kinds of launch edge,hold check There are also four situations , The tightest thing is launch and capture clock All in 20ns moment , amount to 0ns The moment of .

The above example assumes data path The length exceeds 1 individual CLKP The clock period of , Then you need to set multicycle path Give Way setup check Of launch edge One in advance CLKP The clock period of , Pictured 9.

set_multicycle_path 2 -setup \
-from [get_clocks CLKP] -to [get_clocks CLKM] -start

chart 9

This corresponds to hold check launch stay 15ns,capture clock stay 20ns, Need to put hold check Of launch edge Delay one clock cycle , namely launch clock and capture clock All in 20ns It's about , Equivalent to the 0ns for hold check, Pictured 10 Set as follows .