Verilog之数码管译码

参考文献：https://www.runoob.com/w3cnote/verilog-function.html

一、代码修改

参考文献中的测试代码有些不理解，自己稍作修改。四个数码管用abcdefg_x来分别表示。这里附上digital_tube代码

digital_tube.v

`timescale 1ns/1ns;

module digital_tube(
    input               clk,
    input               rstn,
    input               en,

    input [3:0]         single_digit,
    input [3:0]         ten_digit,
    input [3:0]         hundred_digit,
    input [3:0]         kilo_digit,

    output reg [6:0]    abcdefg_1,    //light control
    output reg [6:0]    abcdefg_2,
    output reg [6:0]    abcdefg_3,
    output reg [6:0]    abcdefg_4
);

    always @(posedge clk or negedge rstn) begin
        if(!rstn) begin
            abcdefg_1 <= 7'd0;
            abcdefg_2 <= 7'd0;
            abcdefg_3 <= 7'd0;
            abcdefg_4 <= 7'd0;
        end
        else if(en) begin
            abcdefg_1  <= dt_translate(single_digit);
            abcdefg_2  <= dt_translate(ten_digit);
            abcdefg_3  <= dt_translate(hundred_digit);
            abcdefg_4  <= dt_translate(kilo_digit);
        end
    end

    // translate function
    function [6:0]  dt_translate;
        input [3:0] data;
        begin
            case(data)
                4'd0:     dt_translate = 7'b1111110;     //number 0 -> 0x7e
                4'd1:     dt_translate = 7'b0110000;     //number 1 -> 0x30
                4'd2:     dt_translate = 7'b1101101;     //number 2 -> 0x6d
                4'd3:     dt_translate = 7'b1111001;     //number 3 -> 0x79
                4'd4:     dt_translate = 7'b0110011;     //number 4 -> 0x33
                4'd5:     dt_translate = 7'b1011011;     //number 5 -> 0x5b
                4'd6:     dt_translate = 7'b1011111;     //number 6 -> 0x5f
                4'd7:     dt_translate = 7'b1110000;     //number 7 -> 0x70
                4'd8:     dt_translate = 7'b1111111;     //number 8 -> 0x7f
                4'd9:     dt_translate = 7'b1111011;     //number 9 -> 0x7b
            endcase
        end
    endfunction

    initial begin
        $vcdpluson;
    end
endmodule

自己修改的test.v文件

`timescale 1ns/1ns

module test;
    reg clk;
    reg rstn;
    reg en;

    reg   [3:0]   single_digit;
    reg   [3:0]   ten_digit;
    reg   [3:0]   hundred_digit;
    reg   [3:0]   kilo_digit;

    wire  [3:0]   abcdefg_1;
    wire  [3:0]   abcdefg_2;
    wire  [3:0]   abcdefg_3;
    wire  [3:0]   abcdefg_4;

    integer    i    = 0;
    integer    temp = 0;
    digital_tube digit(
            .clk            (clk),
            .rstn           (rstn),
            .en             (en),
            .single_digit   (single_digit),
            .ten_digit      (ten_digit),
            .hundred_digit  (hundred_digit),
            .kilo_digit     (kilo_digit),

            .abcdefg_1      (abcdefg_1),
            .abcdefg_2      (abcdefg_2),
            .abcdefg_3      (abcdefg_3),
            .abcdefg_4      (abcdefg_4)
    );

    initial begin
        
        for(i = 0; i < 9999; i = i + 1) begin
            single_digit  <= (i % 10);
            ten_digit     <= ((i % 100) / 10);
            hundred_digit <= ((i % 1000) / 100);
            kilo_digit    <= (i / 1000);
            #2;
        end
    end

    initial begin
        clk  = 1'b0;
        rstn = 1'b0;
        en   = 1'b0;
        forever begin
            #1;
            clk = ~clk;
            if ($time > 5000) begin
                $finish;
            end
        end
    end

    initial begin
        #1;
        rstn = 1'b1;
        en   = 1'b1;
    end

    initial begin
        $vcdpluson;
    end
endmodule

显示了从0到9999的显示过程，每个数字显示两个时间单位

二、运行结果

1. 全局图
   由波形图可以看出数据的变化确实如我们所预想。

2) 一个十进制
定位到一个进位波形图

1. 能看到abcdefg_x代表4个数码管。
2. 按照要求依次增加一个数。