Uvm:field automation mechanism

---

Translation domain automation mechanism , This mechanism can be understood as ： about transaction extends uvm_sequence_item, Use uvm_field Macro registered transaction attribute , You can use some uvm Built in method

1. uvm_field Macro registration

field automation The mechanism needs to be used before use uvm_field Macro to register , Different data structures have different registration methods

Pay attention to use uvm_field Before macro registration , Need to be right transaction Conduct factory register , One transaction Examples are as follows

class transaction extends uvm_sequence_item;
	rand bit [47:0] dmac;
	rand bit [47:0] smac;
	rand bit [15:0] ether_type;
	rand byte		pload[];
	rand bit [31:0] crc;
	constraint c{
    pload.size() > 46;pload.size() <512;}
	function new(string name = "transaction");					//uvm_object Of new Function without parent Parameters 
		super.new(name);
	endfunction

	`uvm_object_utils_begin(transaction)
		`uvm_field_int(dmac, UVM_ALL_ON)
		`uvm_field_int(smac, UVM_ALL_ON)
		`uvm_field_int(dmac, UVM_ALL_ON)
		`uvm_field_int(eth_type, UVM_ALL_ON)
		`uvm_field_array_int(pload, UVM_ALL_ON)
	`uvm_object_utils_end
endclass

Registration of variables

for example int, real, enumeration , Inherited from uvm_object class , Events and strings are registered as follows ：

// ARG Represents the object name ,FLAG The flag bit can control the ARG What methods can be used 
`define uvm_field_int(ARG,FLAG)
`define uvm_field_real(ARG,FLAG)
`define uvm_field_enum(T,ARG,FLAG)			//T Represents the enumeration type name 
`define uvm_field_object(ARG,FLAG)
`define uvm_field_event(ARG,FLAG)
`define uvm_field_string(ARG,FLAG)

Dynamic array registration

`define uvm_field_array_int(ARG,FLAG)
`define uvm_field_array_enum(ARG,FLAG)	
`define uvm_field_array_object(ARG,FLAG)
`define uvm_field_array_string(ARG,FLAG)

Registration of static arrays

`define uvm_field_sarray_int(ARG,FLAG)
`define uvm_field_sarray_enum(ARG,FLAG)	
`define uvm_field_sarray_object(ARG,FLAG)
`define uvm_field_sarray_string(ARG,FLAG)

Registration of queues

`define uvm_field_queue_int(ARG,FLAG)
`define uvm_field_queue_enum(ARG,FLAG)	
`define uvm_field_queue_object(ARG,FLAG)
`define uvm_field_queue_string(ARG,FLAG)

Registration of associative arrays

Associative array , Be similar to STL Medium unordered_map

// The format is  `define uvm_field_aa_ Value type _ Key type ( Variable ,FLAG)
`define uvm_field_aa_int_string(ARG,FLAG)
`define uvm_field_aa_string_string(ARG,FLAG)	
`define uvm_field_aa_object_string(ARG,FLAG)

`define uvm_field_aa_int_int(ARG,FLAG)
`define uvm_field_aa_int_int_unsigned(ARG,FLAG)
`define uvm_field_aa_int_integer(ARG,FLAG)
`define uvm_field_aa_int_integer_unsigned(ARG,FLAG)
`define uvm_field_aa_int_byte(ARG,FLAG)
`define uvm_field_aa_int_byte_unsigned(ARG,FLAG)
`define uvm_field_aa_int_shortint(ARG,FLAG)
`define uvm_field_aa_int_shortint_unsigned(ARG,FLAG)
`define uvm_field_aa_int_longint(ARG,FLAG)
`define uvm_field_aa_int_longint_unsigned(ARG,FLAG)

`define uvm_field_aa_int_key(ARG,FLAG)										// Any shape as a key 
`define uvm_field_aa_int_enumkey(ARG,FLAG)									// Any enumeration as a key 

`define uvm_field_aa_string_int(ARG,FLAG)
`define uvm_field_aa_object_int(ARG,FLAG)

1.1. uvm_field Flag bit at the time of registration FLAG

The flag bit refers to the operation uvm_field In macro registration FLAG Parameters , This parameter determines what can be used by the variable uvm_field Method .

for example

`uvm_object_utils_begin(transaction)
	`uvm_field_int(dmac, UVM_ALL_ON)	// here FLAG Take UVM_ALL_ON Indicates that any... Can be used uvm_field Method 
`uvm_object_utils_end

FLAG The essence is to write a 17bit Of parameter Constant , Each of the constants bit Both represent whether or not a certain is allowed to be used uvm_field Method

this 17bit Is defined as follows

//A=ABSTRACT Y=PHYSICAL
//F=REFERENCE, S=SHALLOW, D=DEEP
//K=PACK, R=RECORD, P=PRINT, M=COMPARE, C=COPY
//---------------------- A Y F S D K R P M C
parameter UVM_ALL_ON = 'b0 0 0 0 0 0 1 0 1 0 1 0 1 0 1;			// List only 15bit, for example 0bit decision copy() Whether the method is on ,1bit decision nocopy() Whether the method is on 
parameter UVM_COPY = 		(1<<0);
parameter UVM_NOCOPY = 		(1<<1);
parameter UVM_COMPARE = 	(1<<2);
parameter UVM_NOCOMPARE = 	(1<<3);
parameter UVM_PRINT = 		(1<<4);
parameter UVM_NOPRINT = 	(1<<5);
parameter UVM_RECORD = 		(1<<6);
parameter UVM_NORECORD = 	(1<<7);
parameter UVM_PACK = 		(1<<8);
parameter UVM_NOPACK = 		(1<<9);

So if you want to disable which method , Just match the constants that disable this method with UVM_ALL_ON phase or that will do , It's essentially UVM_ALL_ON When the method is disabled bit Set up 1.

for example

`uvm_object_utils_begin(transaction)
	`uvm_field_int(dmac, UVM_ALL_ON | UVM_NOPACK)	// namely UVM_ALL_ON Of bit5 Set up 1,PACK Method is disabled ,bit4 Of PACK Even for 1 It doesn't work 
`uvm_object_utils_end

Here's how field automation A list of flag bits for

copy relevant

UVM_COPY						// Domains can be replicated （ Default ）
UVM_NOCOPY						// Domain cannot be replicated 
UVM_DEEP						// Domain can be deeply replicated , Object should implement copy() Method （ Default ）
UVM_SHALLOW						// Domains can be shallow replicated 
UVM_REFERENCE					// Fields can only be assigned handles 

compare relevant

UVM_COMPARE						// Domains can be compared （ Default ）
UVM_NOCOMPARE					// Fields cannot be compared 

print relevant

UVM_PRINT						// Fields can be printed （ Default ）
UVM_NOPRINT						// Fields cannot be printed 
UVM_NODEFPRINT					// If the field is equal to the default value , Cannot be printed 
UVM_BIN							// When printing this field , String output format 
UVM_DEC
UVM_UNSIGNED
UVM_OCT
UVM_HEX
UVM_STRING
UVM_TIME
UVM_ENUM

record relevant

UVM_RECORD						// Fields can be automatically recorded （ Default ）
UVM_NORECORD					// Fields cannot be automatically logged 

pack relevant

UVM_PACK						// Domains can be automatically packaged （ Default ）
UVM_NOPACK						// Domains cannot be automatically packaged 

other

UVM_DEEP						// Domain can be used for deep regression operation （copy, compare, print, record, pack）
UVM_SHALLOW						// Domain can be used for shallow regression （copy, compare, print, record, pack）
UVM_REFERENCE					// Fields operate only on handles （copy, compare, print, record, pack）
UVM_READONLY					// The domain cannot be automatically configured , read only mode 
UVM_ALL_ON						// The domain can participate in all data operations 
UVM_DEFAULT						// The domain can participate in all default operations , Present and present UVM_ALL_ON Consistent function 

2. uvm_field Common functions

Use uvm_field The registered variables can directly use the following functions , No more my_transaction Manually defined in

copy

Deep copy of existing objects ,uvm_component and uvm_object All can use , Be careful To allocate memory for new objects in advance

Calling method

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_object.svh
extern function void copy (uvm_object rhs);
extern virtual function void do_copy (uvm_object rhs);

class my_sequence extends uvm_sequence;
	my_transaction tr;
	int name;
	`uvm_component_utils_begin(my_sequence)
		`uvm_field_object(tr,UVM_ALL_ON)
		`uvm_field_int(name,UVM_ALL_ON)
	`uvm_component_utils_end
	//...
endclass
initial begin
	my_sequence seq1,seq2;
	seq1 = my_sequence::type_id::create("seq1",null);
	seq2 = my_sequence::type_id::create("seq2",null);
	seq2.copy(seq1);										// take seq1 Copy to seq2
end

Deep copy and shallow copy

stay my_sequence Class , There is a handle tr. So here comes the question , perform copy, Is just copying the handle ？ Or copy the object pointed to by the handle ？

stay Systemverilog This problem has been mentioned in , If it's just seq2.tr = seq1.tr;, namely Copy addresses only , Pointers to both old and new objects point to the same block of memory , It's light copy

If it is

initial begin
	my_transaction tr1;
	tr1 = my_transaction ::type_id::create("tr1");
	tr1.dmac = seq1.tr.dmac;
	//...
	tr1.ethertype = seq1.tr.ethertype;
	seq2.tr = tr1;										// Deep copy 
end

As shown in the figure below , namely The entity to which the old object pointer points , Re copy to the new memory block , And make the pointer of the new object point to it , It's a deep copy

Callback function do_copy

User defined callback function , The execution of the copy After performing do_copy

class my_transaction extends uvm_sequence_item;
	//...
	virtual function void do_copy(uvm_object rhs);
		my_transaction tr;						// stay my_transaction Method definitions within classes 
		$cast(tr,rhs);							// If the parent class handle rhs Pointing to my_transaction or my_transaction Subclass object of , Will tr Point to rhs Object to point to . Otherwise, the report will be wrong 
		if(tr.diameter > 20)
			this.diameter = 20;
	endfunction
endclass

actually , All objects of the same type as input function or task, With the help of $cast complete , It's just like

initial begin 	
parrot b1,b2;
	b1.func(b2);						// This form of approach , The definition paradigm is as follows  
end 

such function or task The definition paradigm of is as follows

class parrot extends bird;								//parrot yes bird Subclasses of  
 	//...
	virtual funtion void func(bird bd); 		
		parrot	p; 		
		$cast(p,bd);
		//... 
	endfunction 
endclass 

compare

Compare whether the two components are the same , After registration, you can a.compare(b); Can also be b.compare(a);, return 0 Represent different , return 1 It means the same

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_object.svh
extern function bit compare (uvm_object rhs, uvm_comparer comparer=null);
extern virtual function bit do_compare (uvm_object  rhs,
                                          uvm_comparer comparer);

After comparison , The system will print out the difference information between the two objects , however In comparison , Appears by default 1 Stop comparing after the first error . So different comparisons , Only print out 1 Different results .

Global comparison of configuration objects uvm_pkg::uvm_default_comparer

You can use the belonging class uvm_comparer A global object of uvm_dafault_comparer Configure default comparisons .

for example uvm_dafault_comparer.show_max = 10; It can be changed to display at most 10 Different messages .

From the source code can also see , stay compare Function source code can be seen . If the function header does not give comparer, Will be given a uvm_default_comparer object

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_object.svh
function bit  uvm_object::compare (uvm_object rhs,uvm_comparer comparer=null);
  //... 
  if(comparer != null) 
    __m_uvm_status_container.comparer = comparer;   else 
    __m_uvm_status_container.comparer = uvm_default_comparer;
    //...
 endfunction

Let's see uvm_default_comparer The class of the object uvm_comparer, There are many properties that can be set

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_comparer.svh
class uvm_comparer;   
//...
 endclass

Callback function do_compare

User defined callback function , The execution of the compare After performing do_compare

print

Print object All fields of , Or by belonging to uvm_printer Class uvm_default_printer Configure the printing method

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_object.svh
extern function void print (uvm_printer printer=null);

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_printer.svh
virtual class uvm_printer;
//...
endclass

initial beign
	drv = my_driver::type_id::create("drv",null);
	drv.print();
	uvm_default_printer = uvm_default_line_printer;				// Line printer 
	drv.print();
	uvm_default_printer = uvm_default_tree_printer;				// Column printer 
	drv.print();
	uvm_default_printer = uvm_default_table_printer;			// Table printer , Is the default printer 
end

Callback function do_print

Callback function uvm_object::do_print() Is a user-defined optional print function . If a callback function is defined , The system will execute after print We'll do it later do_print

pack And unpack

Package all fields of the object into bit The dynamic array , Or will bit Type dynamic array unpacks and assigns new objects

//...\questasim64_2020.1\verilog_src\uvm-1.2\src\base\uvm_object.svh
extern function int pack(ref bit bitstream[], input uvm_packer packer = null);
extern function int unpack(ref bit bitstream[], input uvm_packer packer = null);

virtual function void do_pack(uvm_packer packer);									// Callback function 
virtual function void do_unpack(uvm_packer packer);

Example

initial begin
	my_transaction tr1,tr2;
	bit package[];
	tr1 = my_transaction::type_id::create("tr1");
	tr2 = my_transaction::type_id::create("tr2");
	tr1.dmac = ....;
	//...
	tr1.pack(package);									// take tr1 Each attribute data is represented by bit In the form of package In a dynamic array 
	tr2.unpack(package);								// take package The dynamic array is repackaged into tr2 Attribute data of 
end

pack_bytes And unpack_bytes

The implementation packages or unpacks all fields of the object into byte flow , Deposit in ref byte unsigned bytestream[] in , And returns the total size

Archetype

extern function int pack_bytes(ref byte unsigned bytestream[], input uvm_packer packer = null);
extern function int unpack_bytes(ref byte unsigned bytestream[], input uvm_packer packer = null);

The calling method is for example

unsigned byte dq[$];
size  = tr. pack_bytes(dq) / 8;				// take my_transaction Type of tr The data is packaged into byte And put in dq in 

pack_ints And unpack_ints

Package all fields of the object or Unpack into int flow

extern function int pack_bytes(ref int unsigned intstream[], input uvm_packer packer = null);
extern function int unpack_bytes(ref int unsigned intstream[], input uvm_packer packer = null);