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[Verilog] HDLBits Problem Solution - Circuits/Sequential Logic/Latches and Flip-Flops

2022-08-03 12:11:00 【wjh776a68】

Sequential Logic

Latches and Flip-Flops

D flip-flop
题目链接

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    // copy d to q at every positive edge of clk
    // Clocked always blocks should use non-blocking assignments
    always @ (posedge clk) begin
        q <= d;
    end
endmodule

D flip-flops
题目链接

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk) begin
        q <= d;
    end
endmodule

DFF with reset
题目链接

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk) begin
        if (reset)
        	q <= 0;
        else
            q <= d;
    end
endmodule

DFF with reset value
题目链接

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always @ (negedge clk) begin
        if (reset)
            q <= 8'h34;
        else
            q <= d;
    end
endmodule

DFF with asynchronous reset
题目链接

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk or posedge areset) begin
        if (areset)
            q <= 0;
        else
            q <= d;
    end
endmodule

DFF with byte enable
题目链接

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always @ (posedge clk) begin
        if (~resetn) begin
            q <= 16'b0;
        end
        else begin
            q <= {
    (({
    8{
    byteena[1]}} & d[15:8]) | ({
    8{
    ~byteena[1]}} & q[15:8])), (({
    8{
    byteena[0]}} & d[7:0]) | ({
    8{
    ~byteena[0]}} & q[7:0]))};
        end
    end
endmodule

D Latch
题目链接

module top_module (
    input d, 
    input ena,
    output q);
    reg q_reg;
    assign q = q_reg;
    always @ (*) begin
        if (ena)
            q_reg <= d;
    end
endmodule

DFF
题目链接

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always @ (posedge clk or posedge ar) begin
        if (ar) 
            q <= 0;
        else
        	q <= d;
    end
endmodule

DFF
题目链接

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always @ (posedge clk) begin
        if (r) begin
            q <= 0;
        end
        else begin
            q <= d;
        end
    end
endmodule

DFF + Gate
题目链接

module top_module (
    input clk,
    input in, 
    output out);
    always @ (posedge clk) begin
        out <= (in ^ out); 
    end
endmodule

Mux and DFF
题目链接

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    wire ff_in = L ? r_in : q_in;
    always @ (posedge clk) begin
        Q <= ff_in;
    end
endmodule

Mux and DFF
题目链接

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
	wire ff_in_1 = E ? w : Q;
    wire ff_in = L ? R : ff_in_1;
    always @ (posedge clk) begin
       Q <= ff_in; 
    end
endmodule

DFFs and gates
题目链接

module top_module (
    input clk,
    input x,
    output z
); 
    reg Q_ff1 = 0, Q_ff2 = 0, Q_ff3 = 0;
    wire D_ff1, D_ff2, D_ff3;
    assign D_ff1 = x ^ Q_ff1;
    assign D_ff2 = ~Q_ff2 & x;
    assign D_ff3 = ~Q_ff3 | x;
    assign z = ~(Q_ff1 | Q_ff2 | Q_ff3);
    always @ (posedge clk) begin
        Q_ff1 <= D_ff1;
        Q_ff2 <= D_ff2;
        Q_ff3 <= D_ff3;
    end
endmodule

Create circuit from truth table
题目链接

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    reg Q_old;
    always @ (posedge clk) begin
        case({
    j,k})
            2'b00: Q <= Q_old;
            2'b01: Q <= 0;
            2'b10: Q <= 1;
            2'b11: Q <= ~Q_old;
        endcase
    end
    
    always @ (*) begin
        Q_old <= Q;
    end
endmodule

Detect an edge
题目链接

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] in_old = 8'b0;
    always @ (posedge clk) begin
        pedge <= (in & ~in_old);
        in_old <= in;
    end
endmodule

Detect both edges
题目链接

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] in_old;
    always @ (posedge clk) begin
        anyedge <= in_old ^ in;
        in_old <= in;
    end
endmodule

Edge capture register
题目链接

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out = 32'b0
);
    reg [31:0] in_old = 32'b0;
    //reg reset_old = 0;
    reg [31:0] out_last = 32'b0;
    always @ (posedge clk) begin
        if (reset) begin
            out <= 'b0;
        end
        else begin
            out <= (in_old & ~in) | out_last;
        end
        in_old <= in;
    end
    
    always @ (*) begin
        out_last <= out;
    end
endmodule

Edge capture register
题目链接

module top_module (
    input clk,
    input d,
    output q
);
    reg q_1, q_2;
    assign q = clk ? q_1 : q_2;
    always @ (posedge clk) begin
        q_1 <= d;
    end
    always @ (negedge clk) begin
        q_2 <= d;
    end
endmodule