PLL of IP core

PLL IP Introduction to nuclear

     PLL（Phase Locked Loop, Phase locked loop ） Is the most commonly used IP Nuclear one , It's powerful , You can input to FPGA Arbitrary frequency division of the clock signal 、 frequency doubling 、 Phase adjustment 、 Duty cycle adjustment , So as to output a desired clock .

Altera Medium PLL Analog phase locked loop , Unlike digital PLL, analog PLL has the advantage of high output stability 、 The phase is continuously adjustable 、 The time delay is continuously adjustable ; The disadvantage is that it will lose lock when the temperature is too high or the electromagnetic radiation is too strong .

PLL How it works

                                       PLL Schematic diagram of structural model

1、 First, you need to refer to the clock （ref_clk） Through frequency discrimination （FD） Phase detector （PD） Compare with the clock frequency that needs to be compared , Let's take frequency adjustment as an example , If the reference clock frequency is equal to the clock frequency to be compared, the output of the frequency phase detector is 0, If the reference clock frequency is greater than the clock frequency to be compared, the frequency phase detector outputs a larger proportional value , If the reference clock frequency is less than the clock frequency to be compared, the frequency phase detector outputs a smaller proportional value .

2、 The output of the frequency and phase discriminator is connected to the loop filter （LF） On , Bandwidth used to control noise , Filter out high-frequency noise , Make it stable at a value , It can smooth the waveform with noise . If the waveform jitter before the frequency and phase discriminator is large , The jitter will be reduced after passing through the loop filter , Approaching the average value of the signal .

3、 The output through the loop filter is connected to the voltage controlled oscillator （VCO） On , The output voltage of the loop filter is used to control VCO The size of the output frequency , The higher the output voltage of the loop filter VCO The higher the output frequency , Then the frequency signal is connected to the frequency and phase discriminator as the frequency to be compared .

        If ref_clk The frequency of the reference clock input is not equal to the clock frequency to be compared , The final realization of the system is to make them gradually equal and stable . If ref_clk The frequency of the reference clock is 50MHz, After the whole closed-loop feedback system , Clock frequency of external output of PLL pll_out It's also 50MHz.

PLL frequency doubling

Frequency doubling is in VCO Then directly add a first-class frequency divider , We know ref_clk The frequency of the reference clock input and the clock frequency to be compared will eventually remain equal after passing through the closed-loop feedback system , Add a frequency divider before the clock that needs to be compared , The signal frequency before entering the frequency divider will be a multiple of the clock frequency to be compared ,VCO Post output pll_out The signal frequency is ref_clk Refer to the result of clock doubling .

 PLL frequency division

Frequency division is in ref_clk Add a frequency divider after the reference clock , In this way, the clock frequency that needs to be compared is always the same as ref_clk The frequency of the reference clock after frequency division is equal , stay VCO Post output pll_out The signal is ref_clk Refer to the result of clock frequency division .

PLL Basic configuration

Above we will respectively c0、c1、c2、c3 The output of is set to that of the input clock 2 frequency doubling 、 Enter the of the clock 2 frequency division 、 Input clock phase shift 90°、 The duty cycle of the input clock changes to 20%, Then compare through simulation .

PLL IP Kernel call

End of configuration IP Post nuclear generation pll_ip.ppf pll_ip.qip pll_ip.v pll_ip_inst.v Four files , among pll_ip_inst.v The code is as follows ：

pll_ip	pll_ip_inst (
	.inclk0 ( inclk0_sig ),
	.c0 ( c0_sig ),
	.c1 ( c1_sig ),
	.c2 ( c2_sig ),
	.c3 ( c3_sig ),
	.locked ( locked_sig )
	);

The following are instantiations PLL IP Core and application code writing

module pll
(
  input  wire   sys_clk,       // The system clock 50MHz
  input  wire   sys_rst_n,
  output wire   clk_mul_2,     // The system clock passes  2  Clock after frequency doubling 
  output wire   clk_div,       // The system clock passes  2  The clock after frequency division 
  output wire   clk_pha_90,    // The system clock is phase shifted  90° After the clock 
  output wire   clk_duc_20,    // The system clock becomes duty cycle  20% The clock of 
  output reg    [1:0]  cnt,   
  output wire   locked         // Check whether the PLL is locked , The output clock is stable only when the signal is high 
);
pll_ip	pll_ip_inst (
	.inclk0 ( sys_clk ),
	.c0 ( clk_mul_2 ),
	.c1 ( clk_div ),
	.c2 ( clk_pha_90 ),
	.c3 ( clk_duc_20 ),
	.locked ( locked )
	);

[email protected](posedge clk_div or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
	   cnt <= 2'd0;
	else
	   cnt <= cnt + 1'b1;   

endmodule

PLL IP Nuclear simulation

`timescale 1ns/1ns
module tb_pll();

reg   sys_clk;

wire  clk_mul_2;
wire  clk_div;
wire  clk_pha_90;
wire  clk_duc_20;
wire  locked;


// Initialize the system clock 
initial sys_clk = 1'b1;

//sys_clk: Analog system clock , Every time  10ns  Level flip once , The period is  20ns, The frequency is  50MHz
always #10 sys_clk = ~sys_clk;

pll pll_inst
(
   .sys_clk   (sys_clk),
   .clk_mul_2 (clk_mul_2),
   .clk_div   (clk_div),
   .clk_pha_90(clk_pha_90),
   .clk_duc_20(clk_duc_20),
   .locked    (locked)
);

endmodule

Then add the prepared simulation file to the project , Conduct simulation , Check the waveform .