Understand Chisel language. 28. Chisel advanced finite state machine (2) - Mealy state machine and comparison with Moore state machine

Chisel进阶之有限状态机（二）——MealyThe state machine, andMooreThe contrast of the state machine

An article we introduced the basic on the finite state machine（FSM）,即Moore机,对应的是输出只和当前状态有关的有限状态机,This article we study the output depends on the input state machine,即Mealy有限状态机,By rising along the test examples to elucidate the features,进一步比较Moore机和Mealy机的区别.

Mealy有限状态机

在Moore机中,输出仅依赖于当前状态,This means that the change of the input can be seen as the earliest output change leads to the next clock cycle.If we are to observe changes in an indirect,We need to build a from input to output the combination of logical path.Now let's consider an example of a minimum,边缘检测电路,Before we use a lineChiselThe code describes the rising along the test：

val risingEdge = din & !(RegNext(din))

The figure below is rising above the schematic along the detector：

When the current input is1And on a periodic input is0的时候,The output will maintain a cycle1.Status register is aD触发器,The next state as input,We can also think this is a clock cycle delay unit.The output logic will compare the current state and the current input.此时可以看到,Output is not only dependent on the current state of,Also depends on the input,This means there is a combinational logic path inFSMBetween the input and output,这种FSM就叫做Mealy有限状态机.

Below is a generalMealyMachine schematic：

和Moore类似,寄存器包含了当前的状态state,The next state logic according to the current statestate和当前输入inTo calculate the value of the next statenext_state.Each to the next clock cycle,next_stateWill become the nextstate.而不同的是,Output logic will be based on the current state ofstate和输入in来计算输出out.

Below is edge detection circuitMealyState transition diagram of machine：

Due to the status register contains only oneD触发器,Therefore there are only two possible state,在这个例子中分别为zero和one.因为MealyThe output of the machine not only dependent on the current state of,Also depends on the input,So we can't describe the output as part of the state of circle,But on the transitions between states arrow mark input values（条件）和输出（After the slash）.需要注意的是,Now we will draw from the transformation,Such as the current state ofzero输入也为0那FSMWill remain in the statezero.Only from the statezero到状态one转换时,We rise along theFSMCan generate output1.在状态one下,输入为1的时候输出为0.We only hope every rise along to create a cycle of pulse.

The following is rising along the detectionMealy机的Chisel实现代码：

import chisel3._
import chisel3.util._

class RisingFsm extends Moudle {
    
    val io = IO(new Bundle {
    
        val din = Input(Bool())
        val risingEdge = Output(Bool())
    })
    
    // 两种状态
    val zero :: one :: Nil = Enum(2)
    
    // 状态寄存器
    val stateReg = RegInit(zero)
    
    // 输出的默认值
    io.risingEdge := false.B
    
    // State transition logic and output logic
    switch (stateReg) {
    
        is(zero) {
    
            when(io.din) {
    
                stateReg := one
                io.risingEdge := true.B
            }
        }
        is(one) {
    
            when(!io.din) {
    
                stateReg := zero
            }
        }
    }
}

The code is similar to the previous example,就不过多解释了.It is important to note the output logic is the part of the state transition logic,状态从zero到one的时候输出为true.B,Otherwise the output is the default valuefalse.B.

但是问题来了,We have been in front of the lineChiselCode that implements this rising along the test,With the matureFSMIs really the best solution to realize rising along the test？The hardware consumption is actually the same,Both methods need aDThe trigger is used to store state information,不过FSMThe combination of the logic will be a little more complicated,Because change dependent on the current state and the input.For the feature,单行的ChiselThe code is easier to write and easier to read,It is crucial for us,Therefore the realization of the single is better.

但这并不是说MealyMachine is useless,We just shows aMealyMachine small example.FSMShould be used in more complex circuit inside,For example there are three or more state circuit.

Moore机和MealyMachine contrast

为了阐明Moore机和Mealy机的不同,我们用MooreMachine to realize the edge detection.下图展示了用MooreMachine implementation rise along the test diagram：

The first should be noticed is thatMooreThree kinds of states that need,而MealyMachine only need two states.其中,状态pulsUsed to generate the pulse signal of the single cycle.FSM只会在pulsState for one clock cycle,Then I will be back to statezero或状态one,Waiting for input change again.We use state transition on the arrows in figure label for input conditions,In the state of circle in digital output.

下面是MooreRising along the detection circuit to realize the machine version：

import chisel3._
import chisel3.util._

class RisingMooreFsm extends Module {
    
    val io = IO(new Bundle {
    
        val din = Input(Bool())
        val risingEdge = Output(Bool())
    })
    
    // 三种状态
    val zero :: puls :: one :: Nil = Enum(3)
    
    // 状态寄存器
    val stateReg = RegInit(zero)
    
    // 状态转换逻辑
    switch (stateReg) {
    
        is(zero) {
    
            when(io.din) {
    
                stateReg := puls
            }
        }
        is(puls) {
    
            when(io.din) {
    
                stateReg := one
            } .otherwise {
    
                stateReg := zero
            }
        }
        is(one) {
    
            when(!io.din) {
    
                stateReg := zero
            }
        }
    }
    
    // 输出逻辑
    io.risingEdge := stateReg === puls
}

可以看出,MooreMachine version thanMealyMachine version or a word version with the doubleD触发器,This also caused state transition logic thanMealyMachine version and a version more.

下图是Mealy机和MooreMachine two versions of the rising along the detection of temporal waveform figure：

我们可以看到,MealyThe output of the machine and rising input along very close,而MooreThe output of the machine's rise along the lag one period.我们还可以注意到,MooreMachine of the high level output to maintain the integrity of a clock cycle,而MealyMachine is usually no more than one clock cycle,To the end of the current clock cycle has ended.

通过以上的例子,我们可以发现Mealy机比MooreBetter machine,On the one hand is to use a less state information therefore less logic,On the other hand the response time and no delay,比MooreMachine faster.However, in the design of larger,MealyCombinational logic path can cause some problems in machine.首先FSMThe communication between the chain（The next section will in detail to say）中,The combinational logic becomes a long,另一方面,如果通信FSMForm a loop between,Will lead to a combinational logic circuits,In synchronous can cause errors in the design of.由于MooreCombinational logic circuit with status register in machine cutting,The above problems in communicationMooreMachine doesn't exist.

总的来说,MooreThe construction of machine is more suitable for communication state machine,他们比MealyMachine more robust.We only in the same period of reaction time and its important useMealy机.Like a small circuit,Such as rising along the test,实际上也是Mealy机,也是可以的.

结语

This part of the two articles are introducedChiselIn the two kinds of state machine——Moore机和Mealy机的实现,Comparison of the resource consumption and timing differences between the two,For us to build your own finite state machine is helpful,Also what kind of state machine for the use of guidance is given.The finite state machine is particularly important in the digital design,And only a finite state machine is discussed,The next section will introduce communication state machine,It is state of multiple units together to communicate with each other the result of,敬请期待.