"One week's data collection" - logic gate

List of articles

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Preface

High level and low level are potential values within a specified range , Not a fixed value .
Common positive logic ： The high level is 3.5-5V, The low level is 0-0.3V.

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One 、pandas What is it? ？

Two 、OC door

Gate circuit with open collector , Add the pull-out resistor and power supply to increase the driving capacity

OC Realization ” Line and “ Logic .
OD The door and OC Door principle is the same , One is a triode and the other is MOS tube .

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3、 ... and 、 Tristate gate

The enable terminal is low , Then the upper and lower MOS The pipe is open , therefore T1 Turn on the high level ,T2 Turn on the low level , At this time, the output is based on the input A Reverse output .A=0,T1 Conduction ,Y=1;A=1,T2 Conduction ,Y=0.
The enable terminal is high , There are two upper and lower circuits in the later stage MOS None of the tubes are conducting , Then the output end is not connected with the input end , The output is in high resistance state .

3、 ... and 、 Transmission gate

Four 、cmos Gate circuit and TTL Characteristics of comparison

Four 、 Integrated gate circuit selection

1、 Operating frequency requirements （ Time required for high and low level reversal ）
2、 Input power supply voltage requirements
3、 Power consumption problem
4、 Level reversal requires input voltage
5、 Pay attention to the current （ Input current ） And pull current （ Output current ）