[Verilog quick start of Niuke online question series] ~ shift operation and multiplication

1. VL4 Shift operation and multiplication

1.1 Title Description

It is known that d For one 8 digit , Please output this number in each clock cycle 1/3/7/8, And output a signal to inform the input at this time d It works （d The rising edge of the given signal indicates that the write is valid ）

1.1.1 Signal schematic diagram

1.1.2 Waveform diagram

1.1.3 Input description

Input signal d, clk, rst
type wire
stay testbench in ,clk For cycles 5ns The clock of ,rst Reset for low level

1.1.4 Output description

The output signal input_grant out
type reg

1.2 Their thinking

This question has two points ： One is how to solve multiplication ？ Another is how to ensure the completion of four times of multiplication ？

1、 We usually use shift operation to solve multiplication and division , But it should be noted that , There is a difference between unsigned numbers and signed numbers ：
An unsigned number ===> Move one bit to the left to multiply 2, Shift one bit to the right to divide 2
Signed number ===> You can only move left , Cannot move right , Why? ？ Because if you move to the right , High position compensation 0, That will affect the highest sign bit ！！！

2、 Solve the second problem , That has to be done with a counter . just 2 The bit counter is just right , Ha ha ha ！！！

1.3 Code implementation

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
    //counter
    reg [1:0] cnt;
    always @ (posedge clk or negedge rst) begin
        if(!rst) begin
           cnt <= 2'b00; 
        end
        else begin
           cnt <= cnt + 1'b1; 
        end
    end
    
    reg [7:0] d_reg;
    always @ (posedge clk or negedge rst) begin
        if(!rst) begin
           out <= 11'd0;
            input_grant <= 1'b0;
            d_reg <= 8'd0;
        end
        else begin
            case (cnt)
                2'b00 : begin
                    out <= d;
                    d_reg <= d;
                    input_grant <= 1'b1;
                end
                2'b01 : begin
                    out <= d_reg + (d_reg<<1);
                    input_grant <= 1'b0;
                end
                2'b10 : begin
                    out <= d_reg + (d_reg<<1) + (d_reg<<2);
                    input_grant <= 1'b0;
                end
                2'b11 : begin
                    out <= d_reg<<3;
                    input_grant <= 1'b0;
                end
                default : begin
                    out <= d;
                    input_grant <= 1'b0;
                end
            endcase
        end
    end

//*************code***********//
endmodule

1.4 The test file

To be updated ...

1.5 Simulation waveform

To be updated ...