Network equipment hard core technology insider router Chapter 21 reconfigurable router

in front 20 In this topic , We see that , Routers can be implemented through these methods ：

1. Home router , In general use Broadcom or MTK Of SoC Scheme realization , Such as Broadcom Of BCM7218X, One chip can realize integration Wi-Fi6 and IPTV Functional home router box .
2. Enterprise level ,1Gbps-200Gbps Performance range router , have access to Marvell (Cavium),Broadcom(RMI) Of MIPS or ARM Multi core processor implementation . It can also be used in the future x86+DPDK Realization .
3. Enterprise high-end and operator level ,200G-20T Performance range router , Current general use NP Realization .

We found that , The higher the performance of the router , The less flexible the forwarding chip is . With NP For example ,NP The message processing pipeline of is limited . In practice , There have been such cases ：

Internet enterprises need to send the traffic separated from metro lines to the back end for analysis , Due to the limited performance of a single analyzer , By stream required ( Business flow TCP Quintuples ) Load balancing .

As shown in the figure below ：

among , The number on the right refers to the offset of the beginning of each header field of the packet .

actually , What users expect is , According to the inner layer IP/TCP Shunting packets onto multiple analyzers . But because of the inner layer IP/TCP Encapsulated in 70 After many bytes , And general NP/ASIC The built-in analyzer can only extract the message header 64 Byte parsing , Therefore, it is difficult to realize such a function . For multicore processors , Although there is also a hardware parsing accelerator inside , similarly , For this deep encapsulated tunnel , It is also difficult to deal with .

Now , We need a programmable hardware acceleration unit to realize this function . Engineers have set their sights on a class of reconfigurable devices ——FPGA.

FPGA yes "Field Programmable Gate Array" （ Field programmable gate array ） Abbreviation . The Chinese name of this tongue twister can actually be disassembled into several parts ：

A programmable —— Its processing logic can be modified , Unlike ASIC That is relatively solidified ;

gate array —— Its internal minimum programming allocation unit is gate circuit and trigger , Therefore, it can be programmed to a high degree , Various processing logic can be reconstructed ;

The scene ——FPGA built-in SRAM Store compiled code , It can be upgraded at runtime through software , Complete the upgrade without even restarting ;

Because of these characteristics ,FPGA It is often used to accelerate packet processing in the network , Typically, it is used for the acceleration of routers or firewalls .

For the previously mentioned scenario of metropolitan area network image traffic analysis , Namely FPGA Where it comes in handy . Engineers only need to FPGA Programming , Let it come from 78 Begin to extract the inner layer at byte IP/UDP( Real business address / port ) The quintuple of , Calculation hash after , Send to the corresponding analyzer , You can do it NP And multi-core routers have a difficult task .

because FPGA Reconfigurable features of , Its reconfigurable router is more open , More powerful , It also makes up for the weakness of the performance degradation of multi-core processors when services are superimposed .

You know the most classic reconfigurable FPGA What kind of router is it ？

When the answer is announced tomorrow , Also tell you a router story …