Verilog grammar basics HDL Bits training 08

Circuits:Combinational Logic:Arithmetic Circuits

一、Half adder

Design one and a half adder

• RTL代码

module top_module( 
    input a, b,
    output cout, sum );
    
    assign {
    cout,sum} = a + b;

endmodule

二、Full adder

Design a full adder,Compared with a half adder,Full adder has a carry input

• RTL代码

module top_module( 
    input a, b, cin,
    output cout, sum );
    
    assign {
    cout,sum} = a + b + cin;

endmodule

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三、3-bit binary adder

Design a full adder

• RTL代码

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    
    integer i;
    always @(*)begin
        cout = 0;
        sum = 0;
        for(i=0;i<3;i=i+1)
            if(i==0)
            	{
    cout[0],sum[0]} = a[0] + b[0] +cin;
        	else
            	{
    cout[i],sum[i]} = a[i] + b[i] + cout[i-1];
    end
endmodule

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四、Adder

• RTL代码

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    
    wire [2:0]cout;
    FA FA_inst1( .a(x[0]), .b(y[0]), .cin(1'b0), .cout(cout[0]), .sum(sum[0]) );
    FA FA_inst2( .a(x[1]), .b(y[1]), .cin(cout[0]), .cout(cout[1]), .sum(sum[1]) );
    FA FA_inst3( .a(x[2]), .b(y[2]), .cin(cout[1]), .cout(cout[2]), .sum(sum[2]) );
    FA FA_inst4( .a(x[3]), .b(y[3]), .cin(cout[2]), .cout(sum[4]), .sum(sum[3]) );

endmodule

module FA( 
    input a, b, cin,
    output cout, sum );
    
    assign {
    cout,sum} = a + b + cin;

endmodule

五、Signed addition overflow

The number of design a symbol adder,同时判断是否溢出
判断溢出的方法：The same two addend that high,And unlike and highest

• RTL代码

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
 
    assign s = a + b;
    assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);

endmodule

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六、100-bit binary adder

Design a one hundred - bit binary adder

• RTL代码

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    
    assign {
    cout,sum} = a + b + cin;

endmodule

七、4-digit BCD adder

Use edit good aBCDAdder instantiation of fourBCDCode adder is designed

• RTL代码

module top_module ( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire cout1,cout2,cout3;
    bcd_fadd adder_inst1(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout1), .sum(sum[3:0]) );
    bcd_fadd adder_inst2(.a(a[7:4]), .b(b[7:4]), .cin(cout1), .cout(cout2), .sum(sum[7:4]) );
    bcd_fadd adder_inst3(.a(a[11:8]), .b(b[11:8]), .cin(cout2), .cout(cout3), .sum(sum[11:8]) );
    bcd_fadd adder_inst4(.a(a[15:12]), .b(b[15:12]), .cin(cout3), .cout(cout), .sum(sum[15:12]) );

endmodule

• 仿真波形图