Verilog avoid latch

Verilog avoid Latch

key word ： trigger , Latch

Latch The meaning of

Latch （Latch）, Is a level triggered storage unit , The action of data storage depends on the input clock （ Or enable ） The level value of the signal . Only when the latch is enabled , The output will change with the data input .

When the level signal is invalid , The output signal varies with the input signal , It's like passing the buffer ; When the level is active , The output signal is latched . Any change in the excitation signal , Will directly cause the change of latch output state , It is very likely that oscillation will occur due to the instability of transient characteristics .

The schematic diagram of latch is as follows ：

trigger （flip-flop）, Is an edge sensitive storage unit , The act of storing data （ State transition ） Synchronized by the rising or falling edge of a signal （ Limit the storage unit state transition in a very short time ）.

The schematic diagram of the trigger is as follows ：

register （register）, stay Verilog Variables used to temporarily store the data involved in the operation and the operation results . When a variable is declared as a register , It can be synthesized into triggers , It may also be integrated into Latch, Even wire Type variable . But in most cases we want it to be integrated into triggers , But sometimes due to code writing problems , It will be synthesized into unexpected Latch structure .

Latch The main hazards are ：

• 1） The input state may change many times , It's easy to burr , The uncertainty of the next stage circuit is increased ;
• 2） In most FPGA In the resources of , It may require more resources than triggers to implement Latch structure ;
• 3） The emergence of latches makes the static timing analysis more complex .

Latch It is mostly used for gating clock （clock gating） The control of , In general design , We should avoid Latch The birth of .

if The structure is incomplete

In combinatorial logic , incomplete if - else structure , Will produce latch.

For example, the following model ,if Missing in statement else structure , System default else Branch lower register of q The value of remains unchanged , That is, it has the function of storing data , So register q Will be integrated into latch structure .

example

module module1_latch1(
    input       data,
    input       en ,
    output reg  q) ;
   
    always @(*) begin
        if (en) q = data ;
    end

endmodule

Avoid this latch There are mainly 2 Kind of , One is to complete if-else structure , Or assign an initial value to the signal .

for example , In the model above always sentence , It can be changed into the following two forms ：

example

    // Complete the conditional branch structure    
    always @(*) begin
        if (en)  q = data ;
        else     q = 1'b0 ;
    end

    // Assign initial value to
    always @(*) begin
        q = 1'b0 ;
        if (en) q = data ; // If en It works , rewrite q Value , otherwise q Will remain as 0
    end

But in temporal logic , incomplete if - else structure , Will not produce latch, For example, the following model .

This is because ,q Register has storage function , And its value will change only under the edge of the clock , This is the characteristic of triggers .

example

module module1_ff(
    input       clk ,
    input       data,
    input       en ,
    output reg  q) ;
   
    always @(posedge clk) begin
        if (en) q <= data ;
    end

endmodule

In combinatorial logic , When there are many assignment statements in a conditional statement , The incompleteness of the assignment statement under each branch condition will also produce latch.

In fact, for the logical split of each signal , This is also equivalent to if-else The structure is incomplete , The related register signal lacks the assignment behavior under other conditions . for example ：

example

module module1_latch11(
    input       data1,
    input       data2,
    input       en ,
    output reg  q1 ,
    output reg  q2) ;
   
    always @(*) begin
        if (en)   q1 = data1 ;
        else      q2 = data2 ;
    end

endmodule

This situation can also be avoided by adding complete assignment statements or assigning initial values latch. for example ：

example

    always @(*) begin
        //q1 = 0; q2 = 0 ; // Or right here q1/q2 Assign initial value to
        if (en)  begin
            q1 = data1 ;
            q2 = 1'b0 ;
        end
        else begin
            q1 = 1'b0 ;
            q2 = data2 ;
        end
    end

case The structure is incomplete

case Statements produce Latch The principle of is almost the same as if The sentences are consistent . In combinatorial logic , When case The list of options is incomplete and there is no addition default keyword , Or when multiple assignment statements are incomplete , There will be Latch. for example ：

example

module module1_latch2(
    input       data1,
    input       data2,
    input [1:0] sel ,
    output reg  q ) ;
   
    always @(*) begin
        case(sel)
            2'b00:  q = data1 ;
            2'b01:  q = data2 ;
        endcase
    end

endmodule

Of course , Eliminate such latch The way to do that is 2 Kind of , take case The list of options is complete , Or assign an initial value to the signal .

Complete case Option list , You can list all the options and results , It can also be used. default Keyword instead of other options results .

for example , Above always The statement has the following 2 Two modification methods .

example

    always @(*) begin
        case(sel)
            2'b00:    q = data1 ;
            2'b01:    q = data2 ;
            default:  q = 1'b0 ;
        endcase
    end

    always @(*) begin
        case(sel)
            2'b00:  q = data1 ;
            2'b01:  q = data2 ;
            2'b10, 2'b11 :  
                    q = 1'b0 ;
        endcase
    end

Assign or judge the original signal

In combinatorial logic , If the assignment source of a signal has its own signal , Or there is the logic of the signal itself in the judgment condition , Then there will be latch. Because at this time, the signal also needs to have the storage function , But there is no clock drive . Such problems are if sentence 、case sentence 、 Question mark expressions can appear , for example ：

example

    //signal itself as a part of condition
    reg a, b ;
    always @(*) begin
        if (a & b)  a = 1'b1 ;   //a -> latch
        else a = 1'b0 ;
    end
   
    //signal itself are the assigment source
    reg        c;
    wire [1:0] sel ;
    always @(*) begin
        case(sel)
            2'b00:    c = c ;    //c -> latch
            2'b01:    c = 1'b1 ;
            default:  c = 1'b0 ;
        endcase
    end

    //signal itself as a part of condition in "? expression"
    wire      d, sel2;
    assign    d =  (sel2 && d) ? 1'b0 : 1'b1 ;  //d -> latch

Avoid this Latch Methods , There's only one , That is to avoid this kind of writing in combinatorial logic , Don't assign a value to the signal itself , And do not use the assignment signal itself to participate in the judgment of conditional logic .

for example , If no immediate output is required , The signal can be delayed by one clock cycle and then combined with related logic . The first one mentioned above produces Latch The code of can be described as ：

example

    reg   a, b ;
    reg   a_r ;
   
    always (@posedge clk)
        a_r  <= a ;
       
    always @(*) begin
        if (a_r & b)  a = 1'b1 ;   //there is no latch
        else a = 1'b0 ;
    end

The list of sensitive signals is incomplete

If in combinatorial logic [email protected]() The sensitive list in the block is not complete , There is no trigger when it should be triggered , Then the relevant register will still save the previous output , Thus a latch is generated .

This situation , Complete the sensitive signal or use it directly [email protected](*) Can eliminate latch.

Summary

All in all , To avoid latch The birth of , In combinatorial logic , The following points need to be noted ：

• 1）if-else or case sentence , The structure must be complete
• 2） Do not place the assignment signal at the assignment source , Or conditional judgment
• 3） The list of sensitive signals is recommended to be multi-purpose [email protected](*)