SOC_SD_CLK

1.接口

input       in_TestMode;
input       hclk;
input       hrst_n;
input [7:0] in_clk_divider;      //分频计数
input       in_sd_clk_enable;	 //时钟使能
input       hw_stop_clk;         //受到DMA和读写控制
output      fifo_sd_clk;		 
output reg  out_sd_clk_o;

2.内部信号

reg [7:0]   div_counter;   //分频计数器
wire        divider_0_val;
wire        out_sd_clk_tp;
wire        clk_ena_stop;

3.功能代码

• 是否分频：in_clk_divider 为0时不分频

assign  divider_0_val = (in_clk_divider == 8'b0 );

• 时钟开关

assign  clk_ena_stop  = (!in_sd_clk_enable || hw_stop_clk);

• 不需要分频的时候，out_sd_clk 置零可以降低功耗

[email protected](posedge hclk or negedge hrst_n) begin
    if(!hrst_n)
        out_sd_clk <= 1'b0;
    else if (clk_ena_stop || divider_0_val)
        out_sd_clk <= 1'b0;
    else if (div_counter == in_clk_divider-1)
        out_sd_clk <= ~out_sd_clk;
end

[email protected](posedge hclk or negedge hrst_n) begin
    if(!hrst_n)
        div_counter <= 8'b0;
    else if ( clk_ena_stop || div_0_val)
        div_counter <= 8'b0;
    else begin
        if(div_counter == in_clk_divider-1)
            div_counter <= 8'b0;
        else
            div_counter <= div_counter + 1;
    end
end

• MUX选择电路构成下来电路
  

MX2X2 U1
( 
    .Y(fifo_sd_clk),
    .A(out_sd_clk),     //0 
    .B(hclk ),          //1
    .S0 (divider_0_val)
);

TLATNTSCAX4 U2
(
    .ECK(out_sd_clk_tp),   //out
    .SE(1 'b0),            //1
    .E( !clk_ena_stop),    //s
    .CK(fifo_sd_clk )      //0 
);

MX2X2 U3
(
    .Y(out_sd_clk_dft),
    .A(out_sd_clk_tp ), //0
    .B(hclk ),          //1
    .S(in_TestMode)
);