[Vitis] Code implementation of ZCU102 development board PS-side control PL-side reset

Reference link

ZYNQ Ultrascale+ Howto reset the PL

Code Implementation

  Xilinx officially provides a function for resetting pl, which is located in [platform project]/zynqmp_fsbl/psu_init.c: unsigned long psu_ps_pl_reset_config_data(void), the following function is a simplification of the official function, execute pl_resetn() on the PS sideThe function can control the pl_resetn pin of the MPSOC IP core (see the figure below for the pin location) to reset the PL terminal.

void pl_resetn(){ //Calling this function will set the pl_resetn0 pin of mpsoc to 1 after outputting 0, that is, low-level resetXil_Out32(0XFF0A0054, 0x00000000U);usleep(1);Xil_Out32(0XFF0A0054, 0x80000000U);}