Learn the customization and testing of fpga---ram IP from the bottom structure

List of articles

Series catalog and portal

1、RAM IP The custom of

①、 first page

②、 The second page

③、 The third page

④、 Page four

⑤、 Page 5

2、RAM IP Example and simulation test of

2.1、 Exemplify a RAM IP nucleus

2.2、 The simulation test  

3、 Summary and reference

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Series catalog and portal

       《 Start with the underlying structure FPGA》 Directory and portal

        Customizing one RAM IP Before nuclear , It is strongly recommended that you read ： Start with the underlying structure FPGA----RAM IP Introduction to nuclear and key parameters . In this article , Have been to RAM IP The key factors of nuclear are explained in detail .

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1、RAM IP The custom of

1. After creating a new project , Click on IP Catalog
2. It will appear after clicking IP Catalog page , stay IP Search in the search box of the kernel block
3. According to the screening , Double click to select RAM & ROM nucleus “Block Memory Generator”

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①、 first page

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②、 The second page

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③、 The third page

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④、 Page four

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⑤、 Page 5

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2、RAM IP Example and simulation test of

2.1、 Exemplify a RAM IP nucleus

        Follow the above steps to generate IP after , Copy IP nucleus The self-contained instantiation template .

        

         And then in our RTL In the code , Instantiate to generate a 4*16 Of SDP RAM.

         The RTL No other functions , Only instantiate RAM that will do . 

module test(
	input 			clk,		// Input clock 
	input 	[3:0]	data_in,	// input data 
	input			en_wr,		// Write enable signal 
	input			en_rd,		// Read enable signal 
	input	[3:0]	addr_wr,	// Write the address 		
	input	[2:0]	addr_rd,	// Read the address 
	input			we_wr,		// Write enable 	
	output	[7:0]	data_out	// Output data 
    );

// Exemplification RAM IP nucleus 
ram_w4_d16	ram_w4_d16_inst (
// port A-- Write the port 
	.clka	(clk),   
	.ena	(en_wr),    
	.wea	(we_wr),    
	.addra	(addr_wr),  
	.dina	(data_in),   
// port B-- Read the port   
	.clkb	(clk),   
	.enb	(en_rd),    
	.addrb	(addr_rd),  
	.doutb	(data_out)  
);
	
endmodule

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2.2、 The simulation test  

         Write a testbench, Yes RAM IP Test it .

         Test behavior ： First go to the address 0-15 Write data 0-15, And then from the address 0-7 Read the data （ Because the read data bit width is the write data bit width 2 times , So reading the data once will read 2 Write address data ）.

`timescale 1ns / 1ns

module tb_test();

reg 			clk;		
reg 	[3:0]	data_in;	
reg				en_wr;			
reg				en_rd;			
reg		[3:0]	addr_wr;	
reg		[2:0]	addr_rd;	
reg				we_wr;		
wire	[7:0]	data_out;	

initial begin
	clk = 0;
	en_wr = 0;en_rd = 0;we_wr = 0;
	data_in = 4'd0;
	addr_wr = 4'd0;
	addr_rd = 3'd0;
	
	#110	
	en_wr = 1;we_wr = 1;	// Start writing data 
	repeat(15) begin		// To address 0-15 Write data 0-15
		#10
		data_in = data_in + 1;
		addr_wr = addr_wr + 1;		
	end
	
	#10
	en_wr = 0;				// Stop writing data 
	en_rd = 1;we_wr = 0;	// Start reading data 
	repeat(10) begin		// From address 0-7 Reading data 
		#10	addr_rd = addr_rd + 1;			
	end	
	en_rd = 0;				// Stop reading data 
	#20 $finish;			// End the simulation 	
end

always #5 clk = ~clk;		// Generate clock , cycle 10ns

// Instantiate the tested module test

test	test_inst(
	.clk		(clk		),	
	.data_in	(data_in	),	
	.en_wr		(en_wr		),	
	.en_rd		(en_rd		),	
	.addr_wr	(addr_wr	),	
	.addr_rd	(addr_rd	),	
	.we_wr		(we_wr		),	
	.data_out	(data_out	)	
);

endmodule

        Use vivado Built in simulation tools simulator Run the simulation , The simulation results are as follows ：

         In line with the expected results .

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3、 Summary and reference

• You can see RAM IP The customization of is quite simple , After knowing its parameters , It can be fast 、 It is very convenient to instantiate one that you need RAM modular .
• It's not easy to create , If this article helps you , Please give me more praise 、 Reviews and collections . Your support is the biggest driving force for me to continuously update ！

Reference material 1：Block Memory Generator v8.4