Can Verilog of synthetizable be integrated

1. Summary of integrable and non integrable sentences ：

（1） Structures supported by all integrated tools ：always,assign,begin,end,case,wire,tri,aupply0,supply1,reg,integer,default,for,function,and,nand,or,nor,xor,xnor,buf,not,bufif0,bufif1,notif0,notif1,if,inout,input,instantitation,module,negedge,posedge,operators,output,parameter.
（2） Structures that are not supported by all integrated tools ：time,defparam,$finish,fork,join,initial,delays,UDP,wait.
（3） Some tools support structures that some tools do not support ：casex,casez,wand,triand,wor,trior,real,disable,forever,arrays,memories,repeat,task,while.

2. Principles of establishing a comprehensive model

Make sure that Verilog HDL The comprehensibility of assignment statements , The following points should be noted during modeling ：
（1） Don't use initial.
（2） Don't use #10.
（3） Do not use loop statements with uncertain number of loops , Such as forever、while etc. . When determining the number of cycles, you can use multiple instantiation calls or generate_genvar_endgenerate sentence
（4） Do not use user-defined primitives （UDP Components ）.
（5） Try to design the circuit in synchronous mode .
（6） Unless it is the design of critical path , Generally, the method of calling gate level components to describe the design is not adopted , It is recommended to use behavior statements to complete the design .
（7） use always Process blocks describe combinatorial logic , All input signals shall be listed in the sensitive signal list , Or directly (*).
（8） All internal registers should be able to be reset , In the use of FPGA When implementing the design , The global reset terminal of the device shall be used as the overall reset terminal of the system as far as possible .
（9） Description and modeling of temporal logic , Non blocking assignment should be used whenever possible . Description and modeling of combinatorial logic , You can assign values with blocking , You can also use non blocking assignment . But in the same process block , It is best not to use both blocking and non blocking assignments .
（10） Not in more than one always Assign a value to the same variable in the process block . However, blocking assignment cannot be used for the same assignment object , Non blocking assignment is also used .
（11） If you don't want to deduce variables into latches , Then it must be in if Sentence or case The variable is explicitly assigned in all conditional branches of the statement .
（12） Avoid mixing triggers triggered by rising and falling edges .
（13） The assignment of the same variable cannot be controlled by multiple clocks , Nor can it be subject to two different clock conditions （ Or different clock edges ） control .
（14） To avoid the case Statement x Value or z value , But you can use .

3. It can't be integrated verilog sentence

1、initial Only in test bench Use in , Can't synthesize .
2、events event In sync testbench Is more useful , Can't synthesize .
3、real I won't support it real Synthesis of data types .
4、time I won't support it time Synthesis of data types .
5、force and release I won't support it force and release The synthesis of .
6、assign and deassign No support for reg Data type assign or deassign To synthesize , Support for wire Data type assign or deassign To synthesize .
7、fork join It can't be integrated , You can use non block statements to achieve the same effect .
8、primitives Support the synthesis of gate level primitives , Synthesis of non gate level primitives is not supported .
9、table I won't support it UDP and table The synthesis of .
10、 The same signal in the sensitive list is accompanied by posedge and negedge
Such as ：always @(posedge clk or negedge clk) begin…end
This always Blocks cannot be integrated .
Such as ：always @(posedge clk or negedge rst_n) begin…end
This always Block integrable .
11、 The same reg Variables are defined by more than one always Block drive , It is easy to cause competition and risk
12、 Time delay With # The initial delay cannot be integrated into hardware circuit delay , The synthesis tool ignores all delay codes , But there is no error .
Such as ：a=#10 b;
there #10 Is the delay for simulation , When synthesizing, the synthesis tool will ignore it . in other words , In synthesis, the above formula is equivalent to a=b;
13、 And X、Z Comparison Some people may like to combine data with... In conditional expressions X( or Z) Compare , However, this is not comprehensive , Comprehensive tools also ignore . So make sure the signal has only two states ：0 or 1.