1150_ Makefile learning_ Duplicate name target processing in makefile

    All learning summary ： GitHub - GreyZhang/g_makefile: Learn makefile from all kinds of tutorials on the web. Happy hacking and let's find an common way so we may don't need to touch makefile code any more!

    This is a small problem that I have added in the process of learning , The research method is to write the test directly Makefile For testing . Maybe , The corresponding contents are also clearly stated in the document , But when I don't know much about the system in the early stage, I can start with such small details 、 The accumulation of small knowledge points begins .

    First design one that can work normally makefile：

t1 : p1

p1:

    echo "first p1"

    The effect of the operation is as follows ：

    This time, , What I want to test is if one Makefile There are two identical target Whether it will report an error ？ Add without error , How to deal with ？ So , Add an identical target. Revised as follows ：

t1 : p1

p1:

    echo "first p1"

p1:

    echo "second p1"

    Running effect ：

    look , It can be detected , In addition, in terms of implementation, the latter actually overrides the former . I saw some of the others Makefile, I feel that there will be similar treatment in it , First, do a small test like this , Maybe I will understand others later Makefile Bring some help when .