FPGA parsing B code----serial 3

前言

    No update for two days,Mainly for debuggingBCode time calculator,Just todayBThe time of the code is parsed out.Originally planned to export first1PPS信号,The results were found beforeBCode parsing misses a lot of judgment,So we can only analyze each signal first,才能正确输出1PPS.will now parseBThe process of coding time program is introduced one by one.

第一章：时间顺序

    由于FPGA都是并行计算,So get used to itwhile（1）mates are not so friendly,So I summed up a method of sequential execution,并且BThe reception of codes is also received sequentially,So it must be added to the sequential execution program.

    方案两种：

    （1）接收到两个PStart the timer after the frame,Then judge the status of each frame according to the timer,This comparison relies on the start sum of the timerBcorrectness of the code,So this structure was abandoned;

    （2）Use the falling edge relationship,Delay the falling edge.

    接收BIn the code I used the first2种方法.Let's look at the extension structure first：

reg        resettime_en_d0; 
reg        resettime_en_d1; 
wire       resettime_falling_flag;（第一个下降沿）
wire       resettime_rasing_flag;
assign resettime_falling_flag = (~resettime_en_d0) & resettime_en_d1;
assign resettime_rasing_flag  = (~resettime_en_d1) & resettime_en_d0;
always @(posedge clk or negedge rst_n) begin         
    if (!rst_n) begin
        resettime_en_d0 <= 1'b0;                                  
        resettime_en_d1 <= 1'b0; 
    end                                                      
    else begin                                               
        resettime_en_d0 <= timebeginflag;（source falling edge）                               
        resettime_en_d1 <= resettime_en_d0;
        		  
    end
end

    There is the first falling edge in the middle,Of course, whichever falling edge you use is optional,BEvery falling edge of the code is OK,You can also define the falling edge yourself.

reg        resettime1_en_d0; 
reg        resettime1_en_d1; 
wire       resettime1_falling_flag;（第二个下降沿）
wire       resettime1_rasing_flag;
assign resettime1_falling_flag = (~resettime1_en_d0) & resettime1_en_d1;
assign resettime1_rasing_flag  = (~resettime1_en_d1) & resettime1_en_d0;
always @(posedge clk or negedge rst_n) begin         
    if (!rst_n) begin
        resettime1_en_d0 <= 1'b0;                                  
        resettime1_en_d1 <= 1'b0; 
    end                                                      
    else begin                                               
        resettime1_en_d0 <= resettime_falling_flag;                               
        resettime1_en_d1 <= resettime1_en_d0;
        		  
    end
end

    This creates a falling edge after the falling edge,It can only be done if there is no guarantee that it will not go wrong.Of course, the Great God probably disdains this approach,But this is the fastest and least error-prone way.

    优点：不容易出错,It doesn't take much thoughtFPGAparallel execution rules.

第二章：锁存B码,判断起始P帧

(*noprune*)reg  [3:0]  bcodelevellatch1;
(*noprune*)reg  [3:0]  bcodelevellatch2;

[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)begin
		bcodelevellatch1 <= 1'd0;
		bcodelevellatch2 <= 1'd0;
	end
	else if (resettime_falling_flag == 1'b1)begin      
		bcodelevellatch1 <= bcodelevel;
		bcodelevellatch2 <= bcodelevellatch1;                     
   end
end

    The first is to judge a pulse width in the previous article0 ,1 ,还是P码之后,Create a falling edge that is delayedresettime_falling_flag,Latch the resulting data into latch中.

(*noprune*)reg    bcodereadyflag;
[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		bcodereadyflag <= 1'd0;
	else if (resettime1_falling_flag == 1'b1)begin 
      if((bcodelevellatch1 >= 4'd3)&&(bcodelevellatch2 >= 4'd3))	
	       bcodereadyflag <= 1'd1; 
	   else bcodereadyflag <= 1'd0;
   end		                  
end

    after latching,According to the delayed second falling edge made above,Determine if both latched values ​​are bothP帧.如果是,将标志位置1,If not continue as0.Of course this flag only appears for one cycle.

    至此,BThe starting frame of the code has been judged.

第三章：锁存Bcode each information code

    Collect one firstB码之后,A count variable must be added,因为B码1s一共100个,所以需要将100个BAll code information is latched.

(*noprune*)reg [7:0] bcodebitcnt;  /*synthesis noprune*/
(*noprune*)reg       bcodeflag;
[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)begin
		bcodebitcnt <= 8'd0;  
        bcodeflag	<= 1'd0;	
	end
	else if (bpluse_falling_flag == 1)begin
		bcodebitcnt <= bcodebitcnt + 1'b1; 
		bcodeflag	<= 1'd0;	
	end
	else if (bcodereadyflag == 1)
	   bcodebitcnt  <= 8'd3;
	else if (bcodebitcnt == 8'd101)begin
	   bcodebitcnt  <= 0;
	   bcodeflag	<= 1'd1;
	end
   else begin
      bcodebitcnt <= bcodebitcnt; 	
	  bcodeflag	  <= 1'd0;
	end
end

    分开说明：Bthe falling edge of the code,bcodebitcnt加1,without latching into twoP帧时,This variable keeps increasing,到101时变为0,That is, not detected2个PStore at will at frame time.当检测到bcodereadyflag变为1时,That is, the lock exists in twoP帧时,将cnt变为3,重新进行存储.因为1和2Two bits store twoP帧,So this place becomes3.

    Bthe falling edge of the code,bcodeflag变为0,当存储到101个时,变为1,即100symbols are stored,The next step can be performed,Of course, it is also a high level for one cycle here.

    分析：为啥是101？为啥不是100？当变为101时,The next cycle state changes immediately100了,所以下次BWhen the falling edge of the code comes,不会存储到101inside the unit.

reg        resettime2_en_d0; 
reg        resettime2_en_d1; 
wire       resettime2_falling_flag;
wire       resettime2_rasing_flag;
assign resettime2_falling_flag = (~resettime2_en_d0) & resettime2_en_d1;
assign resettime2_rasing_flag  = (~resettime2_en_d1) & resettime2_en_d0;
always @(posedge clk or negedge rst_n) begin         
    if (!rst_n) begin
        resettime2_en_d0 <= 1'b0;                                  
        resettime2_en_d1 <= 1'b0; 
    end                                                      
    else begin                                               
        resettime2_en_d0 <= resettime1_falling_flag;                               
        resettime2_en_d1 <= resettime2_en_d0;
        		  
    end
end

    One more falling edge is delayed.现在说明5the role of a falling edge.

    第1个下降沿：bcodein.

    第2个下降沿：bpluse_falling_flag,This falling edge is delayedBThe falling edge of the code is one cycle.Bfalling edge of the code.BThe rising edge of the code startstime定时器,BThe falling edge of the code stopstime定时器.此时判断B码的时间,看看是2ms,5ms,还是8ms.Of course, it is not very accurate to judge the time at this time,But every hardware circuit will have delays,这个地方将timeThe judgment time range is expanded,This can be roughly determinedB码的值.

    At the same time the counter will be latchedbcodebitcnt加1,And determine whether to store to100个码元,如果是第100个码元,Set the reception completed flag：bcodeflag.

    第3个下降沿：resettime_falling_flag,锁存BThe two values ​​of the code.

    第4个下降沿：resettime1_falling_flag,锁存Bafter the two values ​​of the code,判断两个BWhether the code is twoP标志位.此时如果两个B码为P标志位,将bcodebitcnt置为3,那么下次BAfter the code is collected, it is put inbcodebitcnt=3的寄存器中（The parallel problem of falling edge is involved here,You can understand it after logical analysis,When writing, you can put which register you want to put,As long as you can receive it right）.

    第5个下降沿：resettime2_falling_flag,将BThe value of the code is stored in bcodebitcnt对应的寄存器中.对应程序如下：

(*noprune*)reg  [3:0]  b_data_rec1;
(*noprune*)reg  [3:0]  b_data_rec2;
(*noprune*)reg  [3:0]  b_data_rec3;
(*noprune*)reg  [3:0]  b_data_rec4;
(*noprune*)reg  [3:0]  b_data_rec5;
(*noprune*)reg  [3:0]  b_data_rec6;
......
(*noprune*)reg  [3:0]  b_data_rec100;

[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)begin
		b_data_rec1 <= 4'd0;
		b_data_rec2 <= 4'd0;
		b_data_rec3 <= 4'd0;
		b_data_rec4 <= 4'd0;
		b_data_rec5 <= 4'd0;
		b_data_rec6 <= 4'd0;
		......
	    b_data_rec100 <= 4'd0;                             
	end            
	else if (resettime2_falling_flag == 1'b1)begin 
      if (bcodereadyflag == 1)begin   
         b_data_rec1 <= 4'd3;
         b_data_rec2 <= 4'd3;		
		end
		if(bcodebitcnt == 8'd3) b_data_rec3  <= bcodelevel;
		if(bcodebitcnt == 8'd4) b_data_rec4  <= bcodelevel;
		if(bcodebitcnt == 8'd5) b_data_rec5  <= bcodelevel;
		if(bcodebitcnt == 8'd6) b_data_rec6  <= bcodelevel;
		......	
        if(bcodebitcnt == 8'd100)b_data_rec50 <= bcodelevel; 
   end
end

   第四章：BUG

    When writing programs there are many effects that are beyond your control,Others are just thesebugJust complete the logic you need.For example, why is it set as written above3,其实是有问题的,It should have been placed below3register example,但是由于FPGAexecution logic problems,The next falling edge is only put in3的寄存器,所以不管怎么说,As long as each state does what you need,就可以了.

    But if you have enough time,Or better notbug.

    程序中还有一个bug,I don't know where yet,But the result was not quite right,So tomorrowKeep getting this stuff done,Only come slowly,急不得！！！

最后：

    Today, I will write to the latch firstB码的值,In fact, the following will be latched directly according to the logic100个值在bcodeflag变为1The corresponding period is calculated in that periodutc时间即可.This program has been written,and can be parsed correctlyB码的utc时间了.The remaining part and the verification part will be written tomorrow！